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https://git.suyu.dev/suyu/dynarmic.git
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ed6ca58058
Fairly self-explanatory, we can leverage the existing IR functions for the purpose of these instructions. In the integer case, we can just insert function pointers into an array and index it, given all comparison primitives exist already for the integer side of things.
355 lines
11 KiB
C++
355 lines
11 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include <array>
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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namespace {
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enum class Comparison {
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EQ,
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GE,
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GT,
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LE,
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LT,
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};
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bool CompareWithZero(ArmTranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm, Comparison type) {
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if (sz == 0b11 || (F && sz != 0b10)) {
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return v.UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return v.UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [&] {
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const auto reg_m = v.ir.GetVector(m);
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const auto zero = v.ir.ZeroVector();
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if (F) {
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switch (type) {
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case Comparison::EQ:
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return v.ir.FPVectorEqual(32, reg_m, zero, false);
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case Comparison::GE:
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return v.ir.FPVectorGreaterEqual(32, reg_m, zero, false);
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case Comparison::GT:
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return v.ir.FPVectorGreater(32, reg_m, zero, false);
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case Comparison::LE:
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return v.ir.FPVectorGreaterEqual(32, zero, reg_m, false);
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case Comparison::LT:
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return v.ir.FPVectorGreater(32, zero, reg_m, false);
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}
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return IR::U128{};
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} else {
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static constexpr std::array fns{
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&IREmitter::VectorEqual,
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&IREmitter::VectorGreaterEqualSigned,
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&IREmitter::VectorGreaterSigned,
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&IREmitter::VectorLessEqualSigned,
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&IREmitter::VectorLessSigned,
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};
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const size_t esize = 8U << sz;
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return (v.ir.*fns[static_cast<size_t>(type)])(esize, reg_m, zero);
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}
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}();
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v.ir.SetVector(d, result);
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return true;
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}
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} // Anonymous namespace
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bool ArmTranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm) {
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if (op + sz >= 3) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [this, m, op, sz] {
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const auto reg_m = ir.GetVector(m);
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const size_t esize = 16U << sz;
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const auto shift = static_cast<u8>(8U << sz);
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// 64-bit regions
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if (op == 0b00) {
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IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, reg_m, shift),
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ir.VectorLogicalShiftLeft(esize, reg_m, shift));
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switch (sz) {
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case 0: // 8-bit elements
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result = ir.VectorShuffleLowHalfwords(result, 0b00011011);
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result = ir.VectorShuffleHighHalfwords(result, 0b00011011);
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break;
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case 1: // 16-bit elements
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result = ir.VectorShuffleLowHalfwords(result, 0b01001110);
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result = ir.VectorShuffleHighHalfwords(result, 0b01001110);
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break;
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}
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return result;
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}
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// 32-bit regions
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if (op == 0b01) {
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IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, reg_m, shift),
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ir.VectorLogicalShiftLeft(esize, reg_m, shift));
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// If dealing with 8-bit elements we'll need to shuffle the bytes in each halfword
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// e.g. Assume the following numbers point out bytes in a 32-bit word, we're essentially
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// changing [3, 2, 1, 0] to [2, 3, 0, 1]
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if (sz == 0) {
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result = ir.VectorShuffleLowHalfwords(result, 0b10110001);
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result = ir.VectorShuffleHighHalfwords(result, 0b10110001);
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}
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return result;
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}
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// 16-bit regions
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return ir.VectorOr(ir.VectorLogicalShiftRight(esize, reg_m, 8),
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ir.VectorLogicalShiftLeft(esize, reg_m, 8));
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}();
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz == 0b11) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [this, m, sz] {
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const auto reg_m = ir.GetVector(m);
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const size_t esize = 8U << sz;
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const auto shifted = ir.VectorArithmeticShiftRight(esize, reg_m, static_cast<u8>(esize));
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const auto xored = ir.VectorEor(reg_m, shifted);
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const auto clz = ir.VectorCountLeadingZeros(esize, xored);
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return ir.VectorSub(esize, clz, ir.VectorBroadcast(esize, I(esize, 1)));
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}();
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz == 0b11) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [this, m, sz] {
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const auto reg_m = ir.GetVector(m);
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const size_t esize = 8U << sz;
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return ir.VectorCountLeadingZeros(esize, reg_m);
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}();
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz != 0b00) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto reg_m = ir.GetVector(m);
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const auto result = ir.VectorPopulationCount(reg_m);
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz != 0b00) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto reg_m = ir.GetVector(m);
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const auto result = ir.VectorNot(reg_m);
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz == 0b11) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const size_t esize = 8U << sz;
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto reg_m = ir.GetVector(m);
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const auto result = ir.VectorSignedSaturatedAbs(esize, reg_m);
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
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if (sz == 0b11) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const size_t esize = 8U << sz;
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto reg_m = ir.GetVector(m);
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const auto result = ir.VectorSignedSaturatedNeg(esize, reg_m);
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VCGT_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::GT);
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}
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bool ArmTranslatorVisitor::asimd_VCGE_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::GE);
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}
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bool ArmTranslatorVisitor::asimd_VCEQ_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::EQ);
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}
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bool ArmTranslatorVisitor::asimd_VCLE_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::LE);
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}
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bool ArmTranslatorVisitor::asimd_VCLT_zero(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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return CompareWithZero(*this, D, sz, Vd, F, Q, M, Vm, Comparison::LT);
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}
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bool ArmTranslatorVisitor::asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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if (sz == 0b11 || (F && sz != 0b10)) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [this, F, m, sz] {
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const auto reg_m = ir.GetVector(m);
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if (F) {
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return ir.FPVectorAbs(32, reg_m);
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}
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const size_t esize = 8U << sz;
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return ir.VectorAbs(esize, reg_m);
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}();
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
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if (sz == 0b11 || (F && sz != 0b10)) {
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return UndefinedInstruction();
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}
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto result = [this, F, m, sz] {
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const auto reg_m = ir.GetVector(m);
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if (F) {
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return ir.FPVectorNeg(32, reg_m);
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}
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const size_t esize = 8U << sz;
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return ir.VectorSub(esize, ir.ZeroVector(), reg_m);
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}();
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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// Swapping the same register results in the same contents.
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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if (d == m) {
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return true;
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}
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if (Q) {
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const auto reg_d = ir.GetVector(d);
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const auto reg_m = ir.GetVector(m);
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ir.SetVector(m, reg_d);
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ir.SetVector(d, reg_m);
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} else {
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const auto reg_d = ir.GetExtendedRegister(d);
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const auto reg_m = ir.GetExtendedRegister(m);
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ir.SetExtendedRegister(m, reg_d);
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ir.SetExtendedRegister(d, reg_m);
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}
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return true;
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}
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} // namespace Dynarmic::A32
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