mirror of
https://git.suyu.dev/suyu/dynarmic.git
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125 lines
3.7 KiB
C++
125 lines
3.7 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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// Register encodings used by MRS and MSR.
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enum class SystemRegisterEncoding : u32 {
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// Counter-timer Physical Count register
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CNTPCT_EL0 = 0b11'011'1110'0000'001,
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// Cache Type Register
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CTR_EL0 = 0b11'011'0000'0000'001,
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// Data Cache Zero ID register
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DCZID_EL0 = 0b11'011'0000'0000'111,
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// Floating-point Control Register
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FPCR = 0b11'011'0100'0100'000,
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// Floating-point Status Register
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FPSR = 0b11'011'0100'0100'001,
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// Read/Write Software Thread ID Register
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TPIDR_EL0 = 0b11'011'1101'0000'010,
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// Read-Only Software Thread ID Register
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TPIDRRO_EL0 = 0b11'011'1101'0000'011,
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};
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bool TranslatorVisitor::HINT([[maybe_unused]] Imm<4> CRm, [[maybe_unused]] Imm<3> op2) {
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return true;
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}
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bool TranslatorVisitor::NOP() {
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return true;
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}
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bool TranslatorVisitor::YIELD() {
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return RaiseException(Exception::Yield);
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}
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bool TranslatorVisitor::WFE() {
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return RaiseException(Exception::WaitForEvent);
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}
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bool TranslatorVisitor::WFI() {
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return RaiseException(Exception::WaitForInterrupt);
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}
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bool TranslatorVisitor::SEV() {
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return RaiseException(Exception::SendEvent);
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}
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bool TranslatorVisitor::SEVL() {
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return RaiseException(Exception::SendEventLocal);
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}
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bool TranslatorVisitor::CLREX(Imm<4> /*CRm*/) {
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ir.ClearExclusive();
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return true;
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}
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bool TranslatorVisitor::DSB(Imm<4> /*CRm*/) {
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ir.DataSynchronizationBarrier();
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return true;
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}
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bool TranslatorVisitor::DMB(Imm<4> /*CRm*/) {
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ir.DataMemoryBarrier();
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return true;
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}
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bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
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const auto sys_reg = concatenate(Imm<1>{1}, o0, op1, CRn, CRm, op2).ZeroExtend<SystemRegisterEncoding>();
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switch (sys_reg) {
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case SystemRegisterEncoding::TPIDR_EL0:
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ir.SetTPIDR(X(64, Rt));
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return true;
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case SystemRegisterEncoding::FPCR:
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ir.SetFPCR(X(32, Rt));
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ir.SetPC(ir.Imm64(ir.current_location->PC() + 4));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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case SystemRegisterEncoding::FPSR:
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ir.SetFPSR(X(32, Rt));
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return true;
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default:
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break;
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}
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return InterpretThisInstruction();
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}
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bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
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const auto sys_reg = concatenate(Imm<1>{1}, o0, op1, CRn, CRm, op2).ZeroExtend<SystemRegisterEncoding>();
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switch (sys_reg) {
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case SystemRegisterEncoding::TPIDR_EL0:
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X(64, Rt, ir.GetTPIDR());
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return true;
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case SystemRegisterEncoding::TPIDRRO_EL0:
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X(64, Rt, ir.GetTPIDRRO());
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return true;
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case SystemRegisterEncoding::DCZID_EL0:
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X(32, Rt, ir.GetDCZID());
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return true;
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case SystemRegisterEncoding::CTR_EL0:
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X(32, Rt, ir.GetCTR());
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return true;
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case SystemRegisterEncoding::CNTPCT_EL0:
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// HACK: Ensure that this is the first instruction in the block it's emitted in, so the cycle count is most up-to-date.
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if (!ir.block.empty()) {
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ir.SetTerm(IR::Term::LinkBlock{*ir.current_location});
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return false;
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}
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X(64, Rt, ir.GetCNTPCT());
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return true;
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case SystemRegisterEncoding::FPCR:
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X(32, Rt, ir.GetFPCR());
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return true;
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case SystemRegisterEncoding::FPSR:
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X(32, Rt, ir.GetFPSR());
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return true;
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}
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return InterpretThisInstruction();
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}
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} // namespace Dynarmic::A64
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