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fb7d33830c
Normalizes includes to be relative to the project root, like the rest of the includes in the project.
121 lines
3.2 KiB
C++
121 lines
3.2 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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// CPS<effect> <iflags>{, #<mode>}
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// CPS #<mode>
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bool ArmTranslatorVisitor::arm_CPS() {
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return InterpretThisInstruction();
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}
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// MRS<c> <Rd>, <spec_reg>
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bool ArmTranslatorVisitor::arm_MRS(Cond cond, Reg d) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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ir.SetRegister(d, ir.GetCpsr());
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return true;
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}
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// MSR<c> <spec_reg>, #<const>
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bool ArmTranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8) {
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ASSERT_MSG(mask != 0, "Decode error");
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if (!ConditionPassed(cond)) {
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return true;
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}
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const bool write_nzcvq = Common::Bit<3>(mask);
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const bool write_g = Common::Bit<2>(mask);
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const bool write_e = Common::Bit<1>(mask);
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const u32 imm32 = ArmExpandImm(rotate, imm8);
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if (write_nzcvq) {
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ir.SetCpsrNZCVQ(ir.Imm32(imm32 & 0xF8000000));
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}
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if (write_g) {
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ir.SetGEFlagsCompressed(ir.Imm32(imm32 & 0x000F0000));
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}
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if (write_e) {
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const bool E = (imm32 & 0x00000200) != 0;
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if (E != ir.current_location.EFlag()) {
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
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return false;
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}
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}
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return true;
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}
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// MSR<c> <spec_reg>, <Rn>
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bool ArmTranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) {
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if (mask == 0) {
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return UnpredictableInstruction();
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}
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const bool write_nzcvq = Common::Bit<3>(mask);
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const bool write_g = Common::Bit<2>(mask);
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const bool write_e = Common::Bit<1>(mask);
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const auto value = ir.GetRegister(n);
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if (!write_e) {
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if (write_nzcvq) {
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ir.SetCpsrNZCVQ(ir.And(value, ir.Imm32(0xF8000000)));
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}
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if (write_g) {
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ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000)));
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}
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} else {
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const u32 cpsr_mask = (write_nzcvq ? 0xF8000000 : 0) | (write_g ? 0x000F0000 : 0) | 0x00000200;
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const auto old_cpsr = ir.And(ir.GetCpsr(), ir.Imm32(~cpsr_mask));
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const auto new_cpsr = ir.And(value, ir.Imm32(cpsr_mask));
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ir.SetCpsr(ir.Or(old_cpsr, new_cpsr));
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ir.PushRSB(ir.current_location.AdvancePC(4));
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ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
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return false;
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}
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return true;
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}
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// RFE{<amode>} <Rn>{!}
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bool ArmTranslatorVisitor::arm_RFE() {
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return InterpretThisInstruction();
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}
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// SETEND <endian_specifier>
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bool ArmTranslatorVisitor::arm_SETEND(bool E) {
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
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return false;
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}
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// SRS{<amode>} SP{!}, #<mode>
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bool ArmTranslatorVisitor::arm_SRS() {
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return InterpretThisInstruction();
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}
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} // namespace Dynarmic::A32
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