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branch.cpp
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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data_processing_addsub.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_bitfield.cpp
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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data_processing_conditional_compare.cpp
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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data_processing_conditional_select.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_crc32.cpp
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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data_processing_logical.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_multiply.cpp
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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data_processing_pcrel.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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data_processing_register.cpp
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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data_processing_shift.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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exception_generating.cpp
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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floating_point_compare.cpp
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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floating_point_conditional_compare.cpp
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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floating_point_conditional_select.cpp
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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floating_point_conversion_fixed_point.cpp
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A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
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floating_point_conversion_integer.cpp
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A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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floating_point_data_processing_one_register.cpp
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A64: Implement FSQRT (scalar)
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2020-04-22 20:46:14 +01:00 |
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floating_point_data_processing_two_register.cpp
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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impl.cpp
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impl: Update PC when raising exception
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2020-04-22 20:46:15 +01:00 |
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impl.h
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A64: Implement SSUBW/SSUBW2
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2020-04-22 20:46:15 +01:00 |
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load_store_exclusive.cpp
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Exclusive fixups
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2020-04-22 20:46:14 +01:00 |
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load_store_load_literal.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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load_store_multiple_structures.cpp
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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load_store_register_immediate.cpp
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A64: NOP immediate variant of PRFM
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2020-04-22 20:46:15 +01:00 |
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load_store_register_pair.cpp
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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load_store_register_register_offset.cpp
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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load_store_register_unprivileged.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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move_wide.cpp
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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2020-04-22 20:44:38 +01:00 |
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simd_aes.cpp
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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simd_copy.cpp
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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simd_crypto_four_register.cpp
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A64: Implement EOR3 and BCAX
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2020-04-22 20:46:15 +01:00 |
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simd_extract.cpp
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A64: Implement EXT
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2020-04-22 20:46:15 +01:00 |
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simd_modified_immediate.cpp
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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simd_permute.cpp
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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simd_scalar_pairwise.cpp
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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simd_scalar_three_same.cpp
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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simd_scalar_two_register_misc.cpp
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A64: Implement REV64
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2020-04-22 20:46:15 +01:00 |
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simd_sha.cpp
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A64: Implement SHA1H
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2020-04-22 20:46:15 +01:00 |
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simd_shift_by_immediate.cpp
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A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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simd_three_different.cpp
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A64: Implement SSUBW/SSUBW2
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2020-04-22 20:46:15 +01:00 |
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simd_three_same.cpp
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A64: Implement FMUL (vector)
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2020-04-22 20:46:15 +01:00 |
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simd_two_register_misc.cpp
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A64: Implement NEG (vector)
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2020-04-22 20:46:15 +01:00 |
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sys_dc.cpp
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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system.cpp
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A64: system: Use an enum class for MRS/MSR register encodings
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2020-04-22 20:46:15 +01:00 |
