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https://git.suyu.dev/suyu/dynarmic.git
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7bb5440507
Generally hash functions shouldn't throw exceptions. It's also a requirement for the standard library-provided hash functions to not throw exceptions. An exception to this rule is made for user-defined specializations, however we can just be consistent with the standard library on this to allow it to play nicer with it. While we're at it, we can also make the std::less specializations noexcpet as well, since they also can't throw.
203 lines
6.3 KiB
C++
203 lines
6.3 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "backend/x64/a32_jitstate.h"
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#include "backend/x64/block_of_code.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "common/common_types.h"
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#include "frontend/A32/location_descriptor.h"
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namespace Dynarmic::BackendX64 {
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/**
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* CPSR Bits
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* =========
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*
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* ARM CPSR flags
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* --------------
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* N bit 31 Negative flag
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* Z bit 30 Zero flag
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* C bit 29 Carry flag
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* V bit 28 oVerflow flag
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* Q bit 27 Saturation flag
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* J bit 24 Jazelle instruction set flag
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* GE bits 16-19 Greater than or Equal flags
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* E bit 9 Data Endianness flag
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* A bit 8 Disable imprecise Aborts
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* I bit 7 Disable IRQ interrupts
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* F bit 6 Disable FIQ interrupts
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* T bit 5 Thumb instruction set flag
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* M bits 0-4 Processor Mode bits
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*
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* x64 LAHF+SETO flags
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* -------------------
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* SF bit 15 Sign flag
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* ZF bit 14 Zero flag
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* AF bit 12 Auxiliary flag
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* PF bit 10 Parity flag
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* CF bit 8 Carry flag
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* OF bit 0 Overflow flag
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*/
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u32 A32JitState::Cpsr() const {
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ASSERT((CPSR_nzcv & ~0xF0000000) == 0);
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ASSERT((CPSR_q & ~1) == 0);
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ASSERT((CPSR_et & ~3) == 0);
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ASSERT((CPSR_jaifm & ~0x010001DF) == 0);
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u32 cpsr = 0;
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// NZCV flags
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cpsr |= CPSR_nzcv;
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// Q flag
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cpsr |= CPSR_q ? 1 << 27 : 0;
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// GE flags
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cpsr |= Common::Bit<31>(CPSR_ge) ? 1 << 19 : 0;
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cpsr |= Common::Bit<23>(CPSR_ge) ? 1 << 18 : 0;
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cpsr |= Common::Bit<15>(CPSR_ge) ? 1 << 17 : 0;
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cpsr |= Common::Bit<7>(CPSR_ge) ? 1 << 16 : 0;
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// E flag, T flag
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cpsr |= Common::Bit<1>(CPSR_et) ? 1 << 9 : 0;
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cpsr |= Common::Bit<0>(CPSR_et) ? 1 << 5 : 0;
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// Other flags
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cpsr |= CPSR_jaifm;
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return cpsr;
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}
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void A32JitState::SetCpsr(u32 cpsr) {
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// NZCV flags
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CPSR_nzcv = cpsr & 0xF0000000;
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// Q flag
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CPSR_q = Common::Bit<27>(cpsr) ? 1 : 0;
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// GE flags
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CPSR_ge = 0;
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CPSR_ge |= Common::Bit<19>(cpsr) ? 0xFF000000 : 0;
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CPSR_ge |= Common::Bit<18>(cpsr) ? 0x00FF0000 : 0;
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CPSR_ge |= Common::Bit<17>(cpsr) ? 0x0000FF00 : 0;
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CPSR_ge |= Common::Bit<16>(cpsr) ? 0x000000FF : 0;
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// E flag, T flag
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CPSR_et = 0;
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CPSR_et |= Common::Bit<9>(cpsr) ? 2 : 0;
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CPSR_et |= Common::Bit<5>(cpsr) ? 1 : 0;
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// Other flags
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CPSR_jaifm = cpsr & 0x07F0FDDF;
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}
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void A32JitState::ResetRSB() {
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rsb_location_descriptors.fill(0xFFFFFFFFFFFFFFFFull);
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rsb_codeptrs.fill(0);
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}
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/**
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* Comparing MXCSR and FPSCR
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* =========================
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*
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* SSE MXCSR exception flags
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* -------------------------
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* PE bit 5 Precision Flag
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* UE bit 4 Underflow Flag
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* OE bit 3 Overflow Flag
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* ZE bit 2 Divide By Zero Flag
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* DE bit 1 Denormal Flag // Appears to only be set when MXCSR.DAZ = 0
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* IE bit 0 Invalid Operation Flag
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*
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* VFP FPSCR cumulative exception bits
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* -----------------------------------
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* IDC bit 7 Input Denormal cumulative exception bit // Only ever set when FPSCR.FTZ = 1
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* IXC bit 4 Inexact cumulative exception bit
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* UFC bit 3 Underflow cumulative exception bit
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* OFC bit 2 Overflow cumulative exception bit
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* DZC bit 1 Division by Zero cumulative exception bit
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* IOC bit 0 Invalid Operation cumulative exception bit
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*
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* SSE MSCSR exception masks
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* -------------------------
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* PM bit 12 Precision Mask
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* UM bit 11 Underflow Mask
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* OM bit 10 Overflow Mask
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* ZM bit 9 Divide By Zero Mask
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* DM bit 8 Denormal Mask
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* IM bit 7 Invalid Operation Mask
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*
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* VFP FPSCR exception trap enables
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* --------------------------------
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* IDE bit 15 Input Denormal exception trap enable
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* IXE bit 12 Inexact exception trap enable
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* UFE bit 11 Underflow exception trap enable
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* OFE bit 10 Overflow exception trap enable
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* DZE bit 9 Division by Zero exception trap enable
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* IOE bit 8 Invalid Operation exception trap enable
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*
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* SSE MXCSR mode bits
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* -------------------
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* FZ bit 15 Flush To Zero
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* DAZ bit 6 Denormals Are Zero
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* RN bits 13-14 Round to {0 = Nearest, 1 = Negative, 2 = Positive, 3 = Zero}
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*
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* VFP FPSCR mode bits
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* -------------------
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* DN bit 25 Default NaN
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* FZ bit 24 Flush to Zero
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* RMode bits 22-23 Round to {0 = Nearest, 1 = Positive, 2 = Negative, 3 = Zero}
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* Stride bits 20-21 Vector stride
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* Len bits 16-18 Vector length
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*/
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// NZCV; QC (ASMID only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits
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constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK;
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constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
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u32 A32JitState::Fpscr() const {
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ASSERT((FPSCR_mode & ~FPSCR_MODE_MASK) == 0);
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ASSERT((FPSCR_nzcv & ~FPSCR_NZCV_MASK) == 0);
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ASSERT((FPSCR_IDC & ~(1 << 7)) == 0);
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ASSERT((FPSCR_UFC & ~(1 << 3)) == 0);
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u32 FPSCR = FPSCR_mode | FPSCR_nzcv;
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FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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FPSCR |= FPSCR_IDC;
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FPSCR |= FPSCR_UFC;
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FPSCR |= fpsr_exc;
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return FPSCR;
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}
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void A32JitState::SetFpscr(u32 FPSCR) {
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old_FPSCR = FPSCR;
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FPSCR_mode = FPSCR & FPSCR_MODE_MASK;
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FPSCR_nzcv = FPSCR & FPSCR_NZCV_MASK;
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guest_MXCSR = 0;
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// Exception masks / enables
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guest_MXCSR |= 0x00001f80; // mask all
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//guest_MXCSR |= (~FPSCR >> 1) & 0b0000010000000; // IM = ~IOE
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//guest_MXCSR |= (~FPSCR >> 7) & 0b0000100000000; // DM = ~IDE
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//guest_MXCSR |= (~FPSCR ) & 0b1111000000000; // PM, UM, OM, ZM = ~IXE, ~UFE, ~OFE, ~DZE
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// RMode
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const std::array<u32, 4> MXCSR_RMode {0x0, 0x4000, 0x2000, 0x6000};
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guest_MXCSR |= MXCSR_RMode[(FPSCR >> 22) & 0x3];
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// Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
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FPSCR_IDC = 0;
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FPSCR_UFC = 0;
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fpsr_exc = FPSCR & 0x9F;
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if (Common::Bit<24>(FPSCR)) {
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// VFP Flush to Zero
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//guest_MXCSR |= (1 << 15); // SSE Flush to Zero
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//guest_MXCSR |= (1 << 6); // SSE Denormals are Zero
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}
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}
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u64 A32JitState::GetUniqueHash() const noexcept {
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return CPSR_et | FPSCR_mode | (static_cast<u64>(Reg[15]) << 32);
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}
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} // namespace Dynarmic::BackendX64
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