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dynarmic/src/frontend/A64
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Lioncash 7ef7def661 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 
Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
2020-04-22 20:46:23 +01:00
..
decoder A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 2020-04-22 20:46:23 +01:00
translate A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 2020-04-22 20:46:23 +01:00
imm.h imm: Add additional bit position checks to Imm::Bits 2020-04-22 20:46:16 +01:00
ir_emitter.cpp IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
ir_emitter.h IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
location_descriptor.cpp General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 2020-04-22 20:44:38 +01:00
location_descriptor.h fp: A64::FPCR -> FP::FPCR 2020-04-22 20:46:21 +01:00
types.cpp General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 2020-04-22 20:44:38 +01:00
types.h General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 2020-04-22 20:44:38 +01:00