mirror of
https://git.suyu.dev/suyu/dynarmic.git
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318 lines
12 KiB
C++
318 lines
12 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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namespace {
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enum class Rounding {
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None,
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Round
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};
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enum class Accumulating {
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None,
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Accumulate
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};
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enum class Signedness {
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Signed,
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Unsigned
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};
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enum class Narrowing {
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Truncation,
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SaturateToUnsigned,
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SaturateToSigned,
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};
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IR::U128 PerformRoundingCorrection(TranslatorVisitor& v, size_t esize, u64 round_value, IR::U128 original, IR::U128 shifted) {
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const IR::U128 round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
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const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(original, round_const), round_const);
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return v.ir.VectorSub(esize, shifted, round_correction);
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}
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bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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Rounding rounding, Accumulating accumulating, Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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const u8 shift_amount = static_cast<u8>(2 * esize) - concatenate(immh, immb).ZeroExtend<u8>();
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const IR::U128 operand = v.V(datasize, Vn);
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IR::U128 result = [&] {
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if (signedness == Signedness::Signed) {
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return v.ir.VectorArithmeticShiftRight(esize, operand, shift_amount);
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}
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return v.ir.VectorLogicalShiftRight(esize, operand, shift_amount);
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}();
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if (rounding == Rounding::Round) {
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const u64 round_value = 1ULL << (shift_amount - 1);
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result = PerformRoundingCorrection(v, esize, round_value, operand, result);
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}
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if (accumulating == Accumulating::Accumulate) {
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const IR::U128 accumulator = v.V(datasize, Vd);
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result = v.ir.VectorAdd(esize, result, accumulator);
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}
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v.V(datasize, Vd, result);
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return true;
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}
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bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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Rounding rounding, Narrowing narrowing, Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>()) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t source_esize = 2 * esize;
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const size_t part = Q ? 1 : 0;
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const u8 shift_amount = static_cast<u8>(source_esize - concatenate(immh, immb).ZeroExtend());
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const IR::U128 operand = v.V(128, Vn);
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IR::U128 wide_result = [&] {
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if (signedness == Signedness::Signed) {
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return v.ir.VectorArithmeticShiftRight(source_esize, operand, shift_amount);
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}
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return v.ir.VectorLogicalShiftRight(source_esize, operand, shift_amount);
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}();
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if (rounding == Rounding::Round) {
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const u64 round_value = 1ULL << (shift_amount - 1);
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wide_result = PerformRoundingCorrection(v, source_esize, round_value, operand, wide_result);
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}
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const IR::U128 result = [&] {
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switch (narrowing) {
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case Narrowing::Truncation:
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return v.ir.VectorNarrow(source_esize, wide_result);
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case Narrowing::SaturateToUnsigned:
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if (signedness == Signedness::Signed) {
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return v.ir.VectorSignedSaturatedNarrowToUnsigned(source_esize, wide_result);
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}
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return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
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case Narrowing::SaturateToSigned:
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ASSERT(signedness == Signedness::Signed);
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return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
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}
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UNREACHABLE();
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return IR::U128{};
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}();
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v.Vpart(64, Vd, part, result);
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return true;
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}
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bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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Signedness signedness) {
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if (immh == 0b0000) {
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return v.DecodeError();
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}
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if (immh.Bit<3>()) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = 64;
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const size_t part = Q ? 1 : 0;
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const u8 shift_amount = concatenate(immh, immb).ZeroExtend<u8>() - static_cast<u8>(esize);
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const IR::U128 operand = v.Vpart(datasize, Vn, part);
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const IR::U128 expanded_operand = [&] {
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if (signedness == Signedness::Signed) {
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return v.ir.VectorSignExtend(esize, operand);
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}
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return v.ir.VectorZeroExtend(esize, operand);
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}();
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const IR::U128 result = v.ir.VectorLogicalShiftLeft(2 * esize, expanded_operand, shift_amount);
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v.V(2 * datasize, Vd, result);
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return true;
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}
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} // Anonymous namespace
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bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, Signedness::Signed);
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}
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bool TranslatorVisitor::SRSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, Signedness::Signed);
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}
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bool TranslatorVisitor::SRSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, Signedness::Signed);
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}
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bool TranslatorVisitor::SSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, Signedness::Signed);
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}
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bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (immh.Bit<3>() && !Q) {
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return ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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const u8 shift_amount = concatenate(immh, immb).ZeroExtend<u8>() - static_cast<u8>(esize);
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const IR::U128 operand = V(datasize, Vn);
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const IR::U128 result = ir.VectorLogicalShiftLeft(esize, operand, shift_amount);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::Truncation, Signedness::Unsigned);
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}
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bool TranslatorVisitor::RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::Truncation, Signedness::Unsigned);
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}
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bool TranslatorVisitor::SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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const size_t shift = concatenate(immh, immb).ZeroExtend() - esize;
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const IR::U128 operand = V(datasize, Vn);
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const IR::U128 shift_vec = ir.VectorBroadcast(esize, I(esize, shift));
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const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand, shift_vec);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToSigned, Signedness::Signed);
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}
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bool TranslatorVisitor::SQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToSigned, Signedness::Signed);
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}
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bool TranslatorVisitor::SQSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed);
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}
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bool TranslatorVisitor::SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed);
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}
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bool TranslatorVisitor::UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Unsigned);
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}
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bool TranslatorVisitor::UQRSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Unsigned);
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}
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bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Signed);
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}
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bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::None, Signedness::Unsigned);
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}
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bool TranslatorVisitor::URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Accumulating::Accumulate, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::None, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftRight(*this, Q, immh, immb, Vn, Vd, Rounding::None, Accumulating::Accumulate, Signedness::Unsigned);
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}
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bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ShiftLeftLong(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned);
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}
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bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend<u8>());
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const u64 mask = shift_amount == esize ? 0 : Common::Ones<u64>(esize) >> shift_amount;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vd);
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const IR::U128 shifted = ir.VectorLogicalShiftRight(esize, operand1, shift_amount);
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const IR::U128 mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
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const IR::U128 result = ir.VectorOr(ir.VectorAnd(operand2, ir.VectorNot(mask_vec)), shifted);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const size_t datasize = Q ? 128 : 64;
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const u8 shift_amount = concatenate(immh, immb).ZeroExtend<u8>() - static_cast<u8>(esize);
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const u64 mask = Common::Ones<u64>(esize) << shift_amount;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vd);
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const IR::U128 shifted = ir.VectorLogicalShiftLeft(esize, operand1, shift_amount);
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const IR::U128 mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
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const IR::U128 result = ir.VectorOr(ir.VectorAnd(operand2, ir.VectorNot(mask_vec)), shifted);
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V(datasize, Vd, result);
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return true;
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}
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} // namespace Dynarmic::A64
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