mirror of
https://git.suyu.dev/suyu/dynarmic.git
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221 lines
7.2 KiB
C++
221 lines
7.2 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <boost/optional.hpp>
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#include "common/fp/rounding_mode.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
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const size_t intsize = sf ? 64 : 32;
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const auto fltsize = FPGetDataSize(type);
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if (!fltsize || *fltsize == 16) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 intval = X(intsize, Rn);
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IR::U32U64 fltval;
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if (intsize == 32 && *fltsize == 32) {
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fltval = ir.FPS32ToSingle(intval, false, true);
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} else if (intsize == 32 && *fltsize == 64) {
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fltval = ir.FPS32ToDouble(intval, false, true);
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} else if (intsize == 64 && *fltsize == 32) {
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fltval = ir.FPS64ToSingle(intval, false, true);
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} else if (intsize == 64 && *fltsize == 64) {
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fltval = ir.FPS64ToDouble(intval, false, true);
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} else {
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UNREACHABLE();
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}
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V_scalar(*fltsize, Vd, fltval);
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return true;
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}
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bool TranslatorVisitor::UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
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const size_t intsize = sf ? 64 : 32;
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const auto fltsize = FPGetDataSize(type);
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if (!fltsize || *fltsize == 16) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 intval = X(intsize, Rn);
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IR::U32U64 fltval;
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if (intsize == 32 && *fltsize == 32) {
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fltval = ir.FPU32ToSingle(intval, false, true);
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} else if (intsize == 32 && *fltsize == 64) {
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fltval = ir.FPU32ToDouble(intval, false, true);
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} else if (intsize == 64 && *fltsize == 32) {
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fltval = ir.FPU64ToSingle(intval, false, true);
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} else if (intsize == 64 && *fltsize == 64) {
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fltval = ir.FPU64ToDouble(intval, false, true);
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} else {
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UNREACHABLE();
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}
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V_scalar(*fltsize, Vd, fltval);
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return true;
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}
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bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm<1> opc_0, size_t n, size_t d) {
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// NOTE:
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// opcode<2:1> == 0b11
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// rmode<1> == 0b0
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const size_t intsize = sf ? 64 : 32;
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size_t fltsize;
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switch (type.ZeroExtend()) {
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case 0b00:
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fltsize = 32;
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break;
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case 0b01:
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fltsize = 64;
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break;
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case 0b10:
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if (rmode_0 != 1) {
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return UnallocatedEncoding();
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}
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fltsize = 128;
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break;
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default:
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case 0b11:
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fltsize = 16;
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return UnallocatedEncoding();
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}
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bool integer_to_float;
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size_t part;
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switch (rmode_0.ZeroExtend()) {
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case 0b0:
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if (fltsize != 16 && fltsize != intsize) {
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return UnallocatedEncoding();
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}
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integer_to_float = opc_0 == 0b1;
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part = 0;
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break;
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default:
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case 0b1:
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if (intsize != 64 || fltsize != 128) {
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return UnallocatedEncoding();
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}
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integer_to_float = opc_0 == 0b1;
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part = 1;
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fltsize = 64;
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break;
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}
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if (integer_to_float) {
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IR::U32U64 intval = X(intsize, static_cast<Reg>(n));
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Vpart_scalar(fltsize, static_cast<Vec>(d), part, intval);
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} else {
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IR::UAny fltval = Vpart_scalar(fltsize, static_cast<Vec>(n), part);
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IR::U32U64 intval = ZeroExtend(fltval, intsize);
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X(intsize, static_cast<Reg>(d), intval);
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}
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return true;
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}
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static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<2> type, Vec Vn, Reg Rd, FP::RoundingMode rounding_mode) {
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const size_t intsize = sf ? 64 : 32;
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const auto fltsize = FPGetDataSize(type);
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if (!fltsize || *fltsize == 16) {
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return v.UnallocatedEncoding();
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}
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const IR::U32U64 fltval = v.V_scalar(*fltsize, Vn);
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IR::U32U64 intval;
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if (intsize == 32 && *fltsize == 32) {
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intval = v.ir.FPSingleToFixedS32(fltval, 0, rounding_mode);
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} else if (intsize == 32 && *fltsize == 64) {
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intval = v.ir.FPDoubleToFixedS32(fltval, 0, rounding_mode);
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} else if (intsize == 64 && *fltsize == 32) {
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intval = v.ir.FPSingleToFixedS64(fltval, 0, rounding_mode);
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} else if (intsize == 64 && *fltsize == 64) {
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intval = v.ir.FPDoubleToFixedS64(fltval, 0, rounding_mode);
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} else {
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UNREACHABLE();
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}
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v.X(intsize, Rd, intval);
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return true;
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}
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static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Imm<2> type, Vec Vn, Reg Rd, FP::RoundingMode rounding_mode) {
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const size_t intsize = sf ? 64 : 32;
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const auto fltsize = FPGetDataSize(type);
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if (!fltsize || *fltsize == 16) {
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return v.UnallocatedEncoding();
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}
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const IR::U32U64 fltval = v.V_scalar(*fltsize, Vn);
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IR::U32U64 intval;
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if (intsize == 32 && *fltsize == 32) {
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intval = v.ir.FPSingleToFixedU32(fltval, 0, rounding_mode);
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} else if (intsize == 32 && *fltsize == 64) {
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intval = v.ir.FPDoubleToFixedU32(fltval, 0, rounding_mode);
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} else if (intsize == 64 && *fltsize == 32) {
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intval = v.ir.FPSingleToFixedU64(fltval, 0, rounding_mode);
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} else if (intsize == 64 && *fltsize == 64) {
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intval = v.ir.FPDoubleToFixedU64(fltval, 0, rounding_mode);
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} else {
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UNREACHABLE();
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}
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v.X(intsize, Rd, intval);
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return true;
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}
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bool TranslatorVisitor::FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertSignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::ToNearest_TieEven);
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}
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bool TranslatorVisitor::FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::ToNearest_TieEven);
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}
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bool TranslatorVisitor::FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertSignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsZero);
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}
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bool TranslatorVisitor::FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsZero);
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}
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bool TranslatorVisitor::FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertSignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::ToNearest_TieAwayFromZero);
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}
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bool TranslatorVisitor::FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::ToNearest_TieAwayFromZero);
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}
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bool TranslatorVisitor::FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertSignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsPlusInfinity);
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}
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bool TranslatorVisitor::FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsPlusInfinity);
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}
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bool TranslatorVisitor::FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertSignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsMinusInfinity);
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}
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bool TranslatorVisitor::FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
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return FloaingPointConvertUnsignedInteger(*this, sf, type, Vn, Rd, FP::RoundingMode::TowardsMinusInfinity);
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}
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} // namespace Dynarmic::A64
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