| .. |
|
branch.cpp
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
data_processing_addsub.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
data_processing_bitfield.cpp
|
A64: Implement EXTR
|
2020-04-22 20:46:12 +01:00 |
|
data_processing_conditional_compare.cpp
|
A64: Implement CCMP (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
data_processing_conditional_select.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
data_processing_crc32.cpp
|
A64: Implement CRC32
|
2020-04-22 20:46:12 +01:00 |
|
data_processing_logical.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
data_processing_multiply.cpp
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
|
data_processing_pcrel.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
data_processing_register.cpp
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
|
data_processing_shift.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
exception_generating.cpp
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
floating_point_compare.cpp
|
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
|
2020-04-22 20:46:13 +01:00 |
|
floating_point_conditional_compare.cpp
|
A64: Implement FCCMPE
|
2020-04-22 20:46:13 +01:00 |
|
floating_point_conditional_select.cpp
|
A64: Implement FCSEL
|
2020-04-22 20:46:13 +01:00 |
|
floating_point_conversion_fixed_point.cpp
|
IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
|
2020-04-22 20:46:19 +01:00 |
|
floating_point_conversion_integer.cpp
|
A64: Implement FCVTMU (scalar)
|
2020-04-22 20:46:19 +01:00 |
|
floating_point_data_processing_one_register.cpp
|
A64: Implement FRINTX, FRINTI (scalar)
|
2020-04-22 20:46:20 +01:00 |
|
floating_point_data_processing_three_register.cpp
|
A64: Implement FNMSUB
|
2020-04-22 20:46:18 +01:00 |
|
floating_point_data_processing_two_register.cpp
|
A64: Implement FMINNM (scalar)
|
2020-04-22 20:46:15 +01:00 |
|
impl.cpp
|
translate: zero extend result in Vpart when storing to lower part of vector
|
2020-04-22 20:46:17 +01:00 |
|
impl.h
|
A64: Implement load/store single structure instructions
|
2020-04-22 20:46:18 +01:00 |
|
load_store_exclusive.cpp
|
Exclusive fixups
|
2020-04-22 20:46:14 +01:00 |
|
load_store_load_literal.cpp
|
A64: Implement LDR (literal, SIMD&FP)
|
2020-04-22 20:46:18 +01:00 |
|
load_store_multiple_structures.cpp
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
|
2020-04-22 20:46:14 +01:00 |
|
load_store_register_immediate.cpp
|
A64: Add missing decoding for PRFM (unscaled offset)
|
2020-04-22 20:46:17 +01:00 |
|
load_store_register_pair.cpp
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
|
2020-04-22 20:44:38 +01:00 |
|
load_store_register_register_offset.cpp
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
|
2020-04-22 20:46:14 +01:00 |
|
load_store_register_unprivileged.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
load_store_single_structure.cpp
|
A64: Implement load/store single structure instructions
|
2020-04-22 20:46:18 +01:00 |
|
move_wide.cpp
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
|
2020-04-22 20:44:38 +01:00 |
|
simd_across_lanes.cpp
|
A64: Implement ADDV
|
2020-04-22 20:46:19 +01:00 |
|
simd_aes.cpp
|
A64: Implement AESD
|
2020-04-22 20:46:13 +01:00 |
|
simd_copy.cpp
|
A64: Implement DUP (element), scalar variant
|
2020-04-22 20:46:14 +01:00 |
|
simd_crypto_four_register.cpp
|
A64: Implement SM3SS1
|
2020-04-22 20:46:16 +01:00 |
|
simd_crypto_three_register.cpp
|
A64: Implement SM3TT2B
|
2020-04-22 20:46:16 +01:00 |
|
simd_extract.cpp
|
A64: Implement EXT
|
2020-04-22 20:46:19 +01:00 |
|
simd_modified_immediate.cpp
|
A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
|
2020-04-22 20:46:15 +01:00 |
|
simd_permute.cpp
|
A64: Implement UZP1 and UZP2
|
2020-04-22 20:46:17 +01:00 |
|
simd_scalar_pairwise.cpp
|
A64: Implement FADDP (scalar)
|
2020-04-22 20:46:19 +01:00 |
|
simd_scalar_shift_by_immediate.cpp
|
simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant
|
2020-04-22 20:46:21 +01:00 |
|
simd_scalar_three_same.cpp
|
A64: Implement FABD in terms of existing IR instructions
|
2020-04-22 20:46:21 +01:00 |
|
simd_scalar_two_register_misc.cpp
|
simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants
|
2020-04-22 20:46:21 +01:00 |
|
simd_sha.cpp
|
A64: Implement SHA256H and SHA256H2
|
2020-04-22 20:46:16 +01:00 |
|
simd_sha512.cpp
|
A64: Implement SM4EKEY
|
2020-04-22 20:46:17 +01:00 |
|
simd_shift_by_immediate.cpp
|
simd_shift_by_immediate: Merge signed/unsigned helper functions
|
2020-04-22 20:46:16 +01:00 |
|
simd_three_different.cpp
|
simd_three_different: Deduplicate common implementations
|
2020-04-22 20:46:19 +01:00 |
|
simd_three_same.cpp
|
A64: Implement FABD in terms of existing IR instructions
|
2020-04-22 20:46:21 +01:00 |
|
simd_two_register_misc.cpp
|
A64: Implement SADDLP
|
2020-04-22 20:46:19 +01:00 |
|
simd_vector_x_indexed_element.cpp
|
A64: Implement MLS (by element)
|
2020-04-22 20:46:16 +01:00 |
|
sys_dc.cpp
|
Correct typo in DataCacheOperation enum
|
2020-04-22 20:46:18 +01:00 |
|
system.cpp
|
system: Ensure value of CNTPCT_EL0 is accurate
|
2020-04-22 20:46:21 +01:00 |
3f602129f4