Merge pull request #500 from lioncash/cbz

A32: Implement Thumb-1's CBZ/CBNZ instructions

src/frontend/A32/decoder/thumb16.h

@@ -116,6 +116,7 @@ std::optional<std::reference_wrapper<const Thumb16Matcher<V>>> DecodeThumb16(u16
         // Branch instructions
         INST(&V::thumb16_BX,             "BX",                       "010001110mmmm000"), // v4T
         INST(&V::thumb16_BLX_reg,        "BLX (reg)",                "010001111mmmm000"), // v5T
+        INST(&V::thumb16_CBZ_CBNZ,       "CBZ/CBNZ",                 "1011o0i1iiiiinnn"), // v6T2
         INST(&V::thumb16_UDF,            "UDF",                      "11011110--------"),
         INST(&V::thumb16_SVC,            "SVC",                      "11011111xxxxxxxx"),
         INST(&V::thumb16_B_t1,           "B (T1)",                   "1101ccccvvvvvvvv"),

src/frontend/A32/disassembler/disassembler_thumb.cpp

@@ -337,6 +337,13 @@ public:
         return fmt::format("blx {}", m);
     }
 
+    std::string thumb16_CBZ_CBNZ(bool nonzero, Imm<1> i, Imm<5> imm5, Reg n) {
+        const char* const name = nonzero ? "cbnz" : "cbz";
+        const u32 imm = concatenate(i, imm5, Imm<1>{0}).ZeroExtend();
+
+        return fmt::format("{} {}, #{}", name, n, imm);
+    }
+
     std::string thumb16_UDF() {
         return fmt::format("udf");
     }

src/frontend/A32/ir_emitter.cpp

@@ -106,6 +106,10 @@ void IREmitter::SetCpsrNZCVQ(const IR::U32& value) {
     Inst(Opcode::A32SetCpsrNZCVQ, value);
 }
 
+void IREmitter::SetCheckBit(const IR::U1& value) {
+    Inst(Opcode::A32SetCheckBit, value);
+}
+
 IR::U1 IREmitter::GetCFlag() {
     return Inst<IR::U1>(Opcode::A32GetCFlag);
 }

src/frontend/A32/ir_emitter.h

@@ -51,6 +51,7 @@ public:
     void SetCpsr(const IR::U32& value);
     void SetCpsrNZCV(const IR::U32& value);
     void SetCpsrNZCVQ(const IR::U32& value);
+    void SetCheckBit(const IR::U1& value);
     IR::U1 GetCFlag();
     void SetNFlag(const IR::U1& value);
     void SetZFlag(const IR::U1& value);

src/frontend/A32/translate/translate_thumb.cpp

@@ -884,6 +884,29 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // CB{N}Z <Rn>, <label>
+    bool thumb16_CBZ_CBNZ(bool nonzero, Imm<1> i, Imm<5> imm5, Reg n) {
+        const u32 imm = concatenate(i, imm5, Imm<1>{0}).ZeroExtend();
+        const IR::U32 rn = ir.GetRegister(n);
+
+        ir.SetCheckBit(ir.IsZero(rn));
+
+        const auto [cond_pass, cond_fail] = [this, imm, nonzero] {
+            const u32 target = ir.PC() + imm;
+            const auto skip = IR::Term::LinkBlock{ir.current_location.AdvancePC(2)};
+            const auto branch = IR::Term::LinkBlock{ir.current_location.AdvancePC(target)};
+
+            if (nonzero) {
+                return std::make_pair(skip, branch);
+            } else {
+                return std::make_pair(branch, skip);
+            }
+        }();
+
+         ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
+        return false;
+    }
+
     bool thumb16_UDF() {
         return InterpretThisInstruction();
     }

src/frontend/ir/microinstruction.cpp

@@ -477,10 +477,15 @@ bool Inst::IsCoprocessorInstruction() const {
     }
 }
 
+bool Inst::IsSetCheckBitOperation() const {
+    return op == Opcode::A32SetCheckBit ||
+           op == Opcode::A64SetCheckBit;
+}
+
 bool Inst::MayHaveSideEffects() const {
     return op == Opcode::PushRSB                        ||
-           op == Opcode::A64SetCheckBit                 ||
            op == Opcode::A64DataCacheOperationRaised    ||
+           IsSetCheckBitOperation()                     ||
            IsBarrier()                                  ||
            CausesCPUException()                         ||
            WritesToCoreRegister()                       ||

src/frontend/ir/microinstruction.h

@@ -99,6 +99,9 @@ public:
     /// Determines whether or not this instruction causes a CPU exception.
     bool CausesCPUException() const;
 
+    /// Determines whether or not this instruction is a SetCheckBit operation.
+    bool IsSetCheckBitOperation() const;
+
     /// Determines whether or not this instruction may have side-effects.
     bool MayHaveSideEffects() const;
 

src/frontend/ir/opcodes.inc

@@ -5,6 +5,7 @@ OPCODE(Identity,                                            Opaque,         Opaq
 OPCODE(Breakpoint,                                          Void,                                                                           )
 
 // A32 Context getters/setters
+A32OPC(SetCheckBit,                                         Void,           U1                                                              )
 A32OPC(GetRegister,                                         U32,            A32Reg                                                          )
 A32OPC(GetExtendedRegister32,                               U32,            A32ExtReg                                                       )
 A32OPC(GetExtendedRegister64,                               U64,            A32ExtReg                                                       )