A32: Implement ARM-mode BFC

This commit is contained in:
Lioncash 2019-04-20 11:11:44 -04:00 committed by MerryMage
parent 7305d13221
commit fab3a59e05
5 changed files with 44 additions and 7 deletions

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@ -164,6 +164,7 @@ INST(arm_STMIB, "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx
INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------") // all
// Miscellaneous instructions
INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2
INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6

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@ -583,6 +583,9 @@ public:
std::string arm_STM_usr() { return "ice"; }
// Miscellaneous instructions
std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
}
std::string arm_CLZ(Cond cond, Reg d, Reg m) {
return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
}

View file

@ -4,10 +4,32 @@
* General Public License version 2 or any later version.
*/
#include "common/bit_util.h"
#include "translate_arm.h"
namespace Dynarmic::A32 {
// BFC<c> <Rd>, #<lsb>, #<width>
bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
if (msb < lsb) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
}
const u32 mask = ~(Common::Ones<u32>(msb - lsb + 1) << lsb);
const IR::U32 operand = ir.GetRegister(d);
const IR::U32 result = ir.And(operand, ir.Imm32(mask));
ir.SetRegister(d, result);
return true;
}
// CLZ<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
if (d == Reg::PC || m == Reg::PC) {

View file

@ -207,6 +207,7 @@ struct ArmTranslatorVisitor final {
bool arm_STM_usr();
// Miscellaneous instructions
bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
bool arm_CLZ(Cond cond, Reg d, Reg m);
bool arm_NOP() { return true; }
bool arm_RBIT(Cond cond, Reg d, Reg m);