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A32: Implement ARM-mode BFC
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7305d13221
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5 changed files with 44 additions and 7 deletions
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@ -164,6 +164,7 @@ INST(arm_STMIB, "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx
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INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------") // all
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// Miscellaneous instructions
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INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2
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INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
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INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
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INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6
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@ -583,6 +583,9 @@ public:
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std::string arm_STM_usr() { return "ice"; }
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// Miscellaneous instructions
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std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
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return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
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}
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std::string arm_CLZ(Cond cond, Reg d, Reg m) {
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return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
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}
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@ -4,10 +4,32 @@
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "translate_arm.h"
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namespace Dynarmic::A32 {
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// BFC<c> <Rd>, #<lsb>, #<width>
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bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (msb < lsb) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const u32 mask = ~(Common::Ones<u32>(msb - lsb + 1) << lsb);
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const IR::U32 operand = ir.GetRegister(d);
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const IR::U32 result = ir.And(operand, ir.Imm32(mask));
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ir.SetRegister(d, result);
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return true;
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}
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// CLZ<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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@ -207,6 +207,7 @@ struct ArmTranslatorVisitor final {
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bool arm_STM_usr();
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// Miscellaneous instructions
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bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
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bool arm_CLZ(Cond cond, Reg d, Reg m);
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bool arm_NOP() { return true; }
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bool arm_RBIT(Cond cond, Reg d, Reg m);
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