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A32: Implement FastDispatchHint

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This commit is contained in:
MerryMage 2018-09-07 21:30:12 +01:00
parent aa8d826c13
commit f96c43d422
11 changed files with 112 additions and 23 deletions
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4
src/frontend/A32/translate/translate_arm/branch.cpp
View file

@ -52,7 +52,7 @@ bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.BXWritePC(ir.GetRegister(m));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
return true;
@ -65,7 +65,7 @@ bool ArmTranslatorVisitor::arm_BX(Cond cond, Reg m) {
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
return true;

8
src/frontend/A32/translate/translate_arm/load_store.cpp
View file

@ -66,7 +66,7 @@ bool ArmTranslatorVisitor::arm_LDR_lit(Cond cond, bool U, Reg t, Imm12 imm12) {
if (t == Reg::PC) {
ir.LoadWritePC(data);
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
@ -96,7 +96,7 @@ bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n,
if (!P && W && n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
@ -121,7 +121,7 @@ bool ArmTranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n,
if (t == Reg::PC) {
ir.LoadWritePC(data);
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
@ -623,7 +623,7 @@ static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 s
if (n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
return true;

8
src/frontend/A32/translate/translate_thumb.cpp
View file

@ -370,7 +370,7 @@ struct ThumbTranslatorVisitor final {
if (d == Reg::PC) {
ir.ALUWritePC(result.result);
// Return to dispatch as we can't predict what PC is going to be. Stop compilation.
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
} else {
ir.SetRegister(d, result.result);
@ -400,7 +400,7 @@ struct ThumbTranslatorVisitor final {
auto result = ir.GetRegister(m);
if (d == Reg::PC) {
ir.ALUWritePC(result);
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
} else {
ir.SetRegister(d, result);
@ -775,7 +775,7 @@ struct ThumbTranslatorVisitor final {
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}
@ -784,7 +784,7 @@ struct ThumbTranslatorVisitor final {
ir.PushRSB(ir.current_location.AdvancePC(2));
ir.BXWritePC(ir.GetRegister(m));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1));
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
}

2
src/frontend/A64/translate/impl/system.cpp
View file

@ -84,7 +84,7 @@ bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, I
case SystemRegisterEncoding::FPCR:
ir.SetFPCR(X(32, Rt));
ir.SetPC(ir.Imm64(ir.current_location->PC() + 4));
ir.SetTerm(IR::Term::ReturnToDispatch{});
ir.SetTerm(IR::Term::FastDispatchHint{});
return false;
case SystemRegisterEncoding::FPSR:
ir.SetFPSR(X(32, Rt));