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https://git.suyu.dev/suyu/dynarmic.git
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Implement Thumb PUSH instruction
This commit is contained in:
MerryMage
parent
9109b226af
commit
f7e3d7b8d2
10 changed files with 191 additions and 54 deletions
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@ -115,9 +115,9 @@ static Dynarmic::UserCallbacks GetUserCallbacks() {
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return user_callbacks;
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}
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struct InstructionGenerator final {
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struct ThumbInstGen final {
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public:
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InstructionGenerator(const char* format, std::function<bool(u16)> is_valid = [](u16){ return true; }) : is_valid(is_valid) {
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ThumbInstGen(const char* format, std::function<bool(u16)> is_valid = [](u16){ return true; }) : is_valid(is_valid) {
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REQUIRE(strlen(format) == 16);
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for (int i = 0; i < 16; i++) {
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@ -138,10 +138,14 @@ public:
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}
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u16 Generate() const {
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u16 inst;
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do {
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u16 random = RandInt<u16>(0, 0xFFFF);
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inst = bits | (random & ~mask);
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} while (!is_valid(inst));
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ASSERT((inst & mask) == bits);
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return inst;
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}
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private:
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@ -223,6 +227,16 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e
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}
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printf("CPSR: %08x %08x %s\n", interp.Cpsr, jit.Cpsr(), interp.Cpsr != jit.Cpsr() ? "*" : "");
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printf("\nInterp Write Records:\n");
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for (auto& record : interp_write_records) {
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printf("%zu [%x] = %llx\n", record.size, record.address, record.data);
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}
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printf("\nJIT Write Records:\n");
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for (auto& record : jit_write_records) {
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printf("%zu [%x] = %llx\n", record.size, record.address, record.data);
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}
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#ifdef _MSC_VER
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__debugbreak();
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#endif
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@ -234,33 +248,35 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e
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}
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TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") {
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const std::array<InstructionGenerator, 23> instructions = {{
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InstructionGenerator("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
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InstructionGenerator("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
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InstructionGenerator("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
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InstructionGenerator("000110oxxxxxxxxx"), // ADD/SUB_reg
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InstructionGenerator("000111oxxxxxxxxx"), // ADD/SUB_imm
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InstructionGenerator("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
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InstructionGenerator("010000ooooxxxxxx"), // Data Processing
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InstructionGenerator("010001000hxxxxxx"), // ADD (high registers)
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InstructionGenerator("0100010101xxxxxx", // CMP (high registers)
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[](u16 inst){ return Dynarmic::Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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InstructionGenerator("0100010110xxxxxx", // CMP (high registers)
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[](u16 inst){ return Dynarmic::Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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InstructionGenerator("010001100hxxxxxx"), // MOV (high registers)
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InstructionGenerator("10110000oxxxxxxx"), // Adjust stack pointer
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InstructionGenerator("10110010ooxxxxxx"), // SXT/UXT
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InstructionGenerator("1011101000xxxxxx"), // REV
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InstructionGenerator("1011101001xxxxxx"), // REV16
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InstructionGenerator("1011101011xxxxxx"), // REVSH
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InstructionGenerator("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
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InstructionGenerator("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
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InstructionGenerator("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
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InstructionGenerator("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
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InstructionGenerator("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
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InstructionGenerator("1011x100xxxxxxxx"), // PUSH/POP (R = 0)
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InstructionGenerator("1100xxxxxxxxxxxx"), // STMIA/LDMIA
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//InstructionGenerator("101101100101x000"), // SETEND
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const std::array<ThumbInstGen, 24> instructions = {{
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ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
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ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
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ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
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ThumbInstGen("010000ooooxxxxxx"), // Data Processing
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ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
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ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
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[](u16 inst){ return Dynarmic::Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
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[](u16 inst){ return Dynarmic::Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
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ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
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ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
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ThumbInstGen("1011101000xxxxxx"), // REV
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ThumbInstGen("1011101001xxxxxx"), // REV16
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ThumbInstGen("1011101011xxxxxx"), // REVSH
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ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
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ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
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ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
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ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
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ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
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ThumbInstGen("10110100xxxxxxxx", // PUSH (R = 0)
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[](u16 inst){ return Dynarmic::Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("10111100xxxxxxxx"), // POP (R = 0)
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ThumbInstGen("1100xxxxxxxxxxxx"), // STMIA/LDMIA
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//ThumbInstGen("101101100101x000"), // SETEND
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}};
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auto instruction_select = [&]() -> u16 {
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@ -283,22 +299,22 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") {
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}
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TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb]") {
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const std::array<InstructionGenerator, 7> instructions = {{
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InstructionGenerator("01000111xmmmm000", // BLX/BX
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[](u16 inst){
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u32 Rm = Dynarmic::Common::Bits<3, 6>(inst);
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return Rm != 15;
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}),
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InstructionGenerator("1010oxxxxxxxxxxx"), // add to pc/sp
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InstructionGenerator("11100xxxxxxxxxxx"), // B
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InstructionGenerator("01000100h0xxxxxx"), // ADD (high registers)
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InstructionGenerator("01000110h0xxxxxx"), // MOV (high registers)
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InstructionGenerator("1101ccccxxxxxxxx", // B<cond>
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[](u16 inst){
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u32 c = Dynarmic::Common::Bits<9, 12>(inst);
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return c < 0b1110; // Don't want SWI or undefined instructions.
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}),
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InstructionGenerator("10110110011x0xxx"), // CPS
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const std::array<ThumbInstGen, 7> instructions = {{
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ThumbInstGen("01000111xmmmm000", // BLX/BX
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[](u16 inst){
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u32 Rm = Dynarmic::Common::Bits<3, 6>(inst);
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return Rm != 15;
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}),
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ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
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ThumbInstGen("11100xxxxxxxxxxx"), // B
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ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
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ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
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ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
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[](u16 inst){
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u32 c = Dynarmic::Common::Bits<9, 12>(inst);
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return c < 0b1110; // Don't want SWI or undefined instructions.
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}),
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ThumbInstGen("10110110011x0xxx"), // CPS
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}};
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auto instruction_select = [&]() -> u16 {
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