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https://git.suyu.dev/suyu/dynarmic.git
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IR: Compile-time type-checking of IR
This commit is contained in:
MerryMage
parent
44f7f04b5c
commit
f61da0b5a9
13 changed files with 697 additions and 618 deletions
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@ -23,230 +23,230 @@ u32 IREmitter::AlignPC(size_t alignment) {
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return static_cast<u32>(pc - pc % alignment);
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}
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IR::Value IREmitter::GetRegister(A32::Reg reg) {
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IR::U32 IREmitter::GetRegister(Reg reg) {
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if (reg == A32::Reg::PC) {
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return Imm32(PC());
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}
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return Inst(Opcode::A32GetRegister, { IR::Value(reg) });
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return Inst<IR::U32>(Opcode::A32GetRegister, IR::Value(reg));
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}
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IR::Value IREmitter::GetExtendedRegister(A32::ExtReg reg) {
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IR::F32F64 IREmitter::GetExtendedRegister(ExtReg reg) {
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if (A32::IsSingleExtReg(reg)) {
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return Inst(Opcode::A32GetExtendedRegister32, {IR::Value(reg)});
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return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
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}
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if (A32::IsDoubleExtReg(reg)) {
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return Inst(Opcode::A32GetExtendedRegister64, {IR::Value(reg)});
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return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
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}
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ASSERT_MSG(false, "Invalid reg.");
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}
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void IREmitter::SetRegister(const A32::Reg reg, const IR::Value& value) {
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void IREmitter::SetRegister(const Reg reg, const IR::U32& value) {
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ASSERT(reg != A32::Reg::PC);
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Inst(Opcode::A32SetRegister, { IR::Value(reg), value });
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Inst(Opcode::A32SetRegister, IR::Value(reg), value);
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}
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void IREmitter::SetExtendedRegister(const A32::ExtReg reg, const IR::Value& value) {
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void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::F32F64& value) {
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if (A32::IsSingleExtReg(reg)) {
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Inst(Opcode::A32SetExtendedRegister32, {IR::Value(reg), value});
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Inst(Opcode::A32SetExtendedRegister32, IR::Value(reg), value);
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} else if (A32::IsDoubleExtReg(reg)) {
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Inst(Opcode::A32SetExtendedRegister64, {IR::Value(reg), value});
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Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
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} else {
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ASSERT_MSG(false, "Invalid reg.");
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}
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}
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void IREmitter::ALUWritePC(const IR::Value& value) {
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void IREmitter::ALUWritePC(const IR::U32& value) {
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// This behaviour is ARM version-dependent.
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// The below implementation is for ARMv6k
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BranchWritePC(value);
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}
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void IREmitter::BranchWritePC(const IR::Value& value) {
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void IREmitter::BranchWritePC(const IR::U32& value) {
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if (!current_location.TFlag()) {
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auto new_pc = And(value, Imm32(0xFFFFFFFC));
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Inst(Opcode::A32SetRegister, { IR::Value(A32::Reg::PC), new_pc });
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Inst(Opcode::A32SetRegister, IR::Value(A32::Reg::PC), new_pc);
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} else {
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auto new_pc = And(value, Imm32(0xFFFFFFFE));
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Inst(Opcode::A32SetRegister, { IR::Value(A32::Reg::PC), new_pc });
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Inst(Opcode::A32SetRegister, IR::Value(A32::Reg::PC), new_pc);
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}
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}
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void IREmitter::BXWritePC(const IR::Value& value) {
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Inst(Opcode::A32BXWritePC, {value});
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void IREmitter::BXWritePC(const IR::U32& value) {
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Inst(Opcode::A32BXWritePC, value);
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}
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void IREmitter::LoadWritePC(const IR::Value& value) {
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void IREmitter::LoadWritePC(const IR::U32& value) {
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// This behaviour is ARM version-dependent.
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// The below implementation is for ARMv6k
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BXWritePC(value);
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}
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void IREmitter::CallSupervisor(const IR::Value& value) {
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Inst(Opcode::A32CallSupervisor, {value});
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void IREmitter::CallSupervisor(const IR::U32& value) {
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Inst(Opcode::A32CallSupervisor, value);
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}
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IR::Value IREmitter::GetCpsr() {
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return Inst(Opcode::A32GetCpsr, {});
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IR::U32 IREmitter::GetCpsr() {
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return Inst<IR::U32>(Opcode::A32GetCpsr);
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}
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void IREmitter::SetCpsr(const IR::Value& value) {
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Inst(Opcode::A32SetCpsr, {value});
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void IREmitter::SetCpsr(const IR::U32& value) {
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Inst(Opcode::A32SetCpsr, value);
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}
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void IREmitter::SetCpsrNZCV(const IR::Value& value) {
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Inst(Opcode::A32SetCpsrNZCV, {value});
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void IREmitter::SetCpsrNZCV(const IR::U32& value) {
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Inst(Opcode::A32SetCpsrNZCV, value);
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}
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void IREmitter::SetCpsrNZCVQ(const IR::Value& value) {
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Inst(Opcode::A32SetCpsrNZCVQ, {value});
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void IREmitter::SetCpsrNZCVQ(const IR::U32& value) {
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Inst(Opcode::A32SetCpsrNZCVQ, value);
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}
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IR::Value IREmitter::GetCFlag() {
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return Inst(Opcode::A32GetCFlag, {});
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IR::U1 IREmitter::GetCFlag() {
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return Inst<IR::U1>(Opcode::A32GetCFlag);
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}
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void IREmitter::SetNFlag(const IR::Value& value) {
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Inst(Opcode::A32SetNFlag, {value});
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void IREmitter::SetNFlag(const IR::U1& value) {
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Inst(Opcode::A32SetNFlag, value);
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}
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void IREmitter::SetZFlag(const IR::Value& value) {
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Inst(Opcode::A32SetZFlag, {value});
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void IREmitter::SetZFlag(const IR::U1& value) {
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Inst(Opcode::A32SetZFlag, value);
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}
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void IREmitter::SetCFlag(const IR::Value& value) {
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Inst(Opcode::A32SetCFlag, {value});
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void IREmitter::SetCFlag(const IR::U1& value) {
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Inst(Opcode::A32SetCFlag, value);
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}
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void IREmitter::SetVFlag(const IR::Value& value) {
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Inst(Opcode::A32SetVFlag, {value});
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void IREmitter::SetVFlag(const IR::U1& value) {
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Inst(Opcode::A32SetVFlag, value);
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}
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void IREmitter::OrQFlag(const IR::Value& value) {
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Inst(Opcode::A32OrQFlag, {value});
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void IREmitter::OrQFlag(const IR::U1& value) {
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Inst(Opcode::A32OrQFlag, value);
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}
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IR::Value IREmitter::GetGEFlags() {
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return Inst(Opcode::A32GetGEFlags, {});
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IR::U32 IREmitter::GetGEFlags() {
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return Inst<IR::U32>(Opcode::A32GetGEFlags);
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}
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void IREmitter::SetGEFlags(const IR::Value& value) {
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Inst(Opcode::A32SetGEFlags, {value});
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void IREmitter::SetGEFlags(const IR::U32& value) {
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Inst(Opcode::A32SetGEFlags, value);
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}
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void IREmitter::SetGEFlagsCompressed(const IR::Value& value) {
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Inst(Opcode::A32SetGEFlagsCompressed, {value});
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void IREmitter::SetGEFlagsCompressed(const IR::U32& value) {
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Inst(Opcode::A32SetGEFlagsCompressed, value);
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}
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IR::Value IREmitter::GetFpscr() {
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return Inst(Opcode::A32GetFpscr, {});
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IR::U32 IREmitter::GetFpscr() {
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return Inst<IR::U32>(Opcode::A32GetFpscr);
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}
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void IREmitter::SetFpscr(const IR::Value& new_fpscr) {
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Inst(Opcode::A32SetFpscr, {new_fpscr});
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void IREmitter::SetFpscr(const IR::U32& new_fpscr) {
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Inst(Opcode::A32SetFpscr, new_fpscr);
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}
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IR::Value IREmitter::GetFpscrNZCV() {
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return Inst(Opcode::A32GetFpscrNZCV, {});
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IR::U32 IREmitter::GetFpscrNZCV() {
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return Inst<IR::U32>(Opcode::A32GetFpscrNZCV);
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}
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void IREmitter::SetFpscrNZCV(const IR::Value& new_fpscr_nzcv) {
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Inst(Opcode::A32SetFpscrNZCV, {new_fpscr_nzcv});
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void IREmitter::SetFpscrNZCV(const IR::U32& new_fpscr_nzcv) {
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Inst(Opcode::A32SetFpscrNZCV, new_fpscr_nzcv);
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}
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void IREmitter::ClearExclusive() {
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Inst(Opcode::A32ClearExclusive, {});
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Inst(Opcode::A32ClearExclusive);
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}
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void IREmitter::SetExclusive(const IR::Value& vaddr, size_t byte_size) {
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void IREmitter::SetExclusive(const IR::U32& vaddr, size_t byte_size) {
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ASSERT(byte_size == 1 || byte_size == 2 || byte_size == 4 || byte_size == 8 || byte_size == 16);
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Inst(Opcode::A32SetExclusive, {vaddr, Imm8(u8(byte_size))});
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Inst(Opcode::A32SetExclusive, vaddr, Imm8(u8(byte_size)));
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}
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IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) {
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return Inst(Opcode::A32ReadMemory8, {vaddr});
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IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr) {
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return Inst<IR::U8>(Opcode::A32ReadMemory8, vaddr);
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}
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IR::Value IREmitter::ReadMemory16(const IR::Value& vaddr) {
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auto value = Inst(Opcode::A32ReadMemory16, {vaddr});
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IR::U16 IREmitter::ReadMemory16(const IR::U32& vaddr) {
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auto value = Inst<IR::U16>(Opcode::A32ReadMemory16, vaddr);
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return current_location.EFlag() ? ByteReverseHalf(value) : value;
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}
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IR::Value IREmitter::ReadMemory32(const IR::Value& vaddr) {
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auto value = Inst(Opcode::A32ReadMemory32, {vaddr});
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IR::U32 IREmitter::ReadMemory32(const IR::U32& vaddr) {
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auto value = Inst<IR::U32>(Opcode::A32ReadMemory32, vaddr);
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return current_location.EFlag() ? ByteReverseWord(value) : value;
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}
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IR::Value IREmitter::ReadMemory64(const IR::Value& vaddr) {
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auto value = Inst(Opcode::A32ReadMemory64, {vaddr});
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IR::U64 IREmitter::ReadMemory64(const IR::U32& vaddr) {
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auto value = Inst<IR::U64>(Opcode::A32ReadMemory64, vaddr);
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return current_location.EFlag() ? ByteReverseDual(value) : value;
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}
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void IREmitter::WriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
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Inst(Opcode::A32WriteMemory8, {vaddr, value});
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void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value) {
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Inst(Opcode::A32WriteMemory8, vaddr, value);
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}
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void IREmitter::WriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
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void IREmitter::WriteMemory16(const IR::U32& vaddr, const IR::U16& value) {
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if (current_location.EFlag()) {
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auto v = ByteReverseHalf(value);
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Inst(Opcode::A32WriteMemory16, {vaddr, v});
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Inst(Opcode::A32WriteMemory16, vaddr, v);
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} else {
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Inst(Opcode::A32WriteMemory16, {vaddr, value});
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Inst(Opcode::A32WriteMemory16, vaddr, value);
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}
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}
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void IREmitter::WriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
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void IREmitter::WriteMemory32(const IR::U32& vaddr, const IR::U32& value) {
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if (current_location.EFlag()) {
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auto v = ByteReverseWord(value);
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Inst(Opcode::A32WriteMemory32, {vaddr, v});
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Inst(Opcode::A32WriteMemory32, vaddr, v);
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} else {
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Inst(Opcode::A32WriteMemory32, {vaddr, value});
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Inst(Opcode::A32WriteMemory32, vaddr, value);
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}
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}
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void IREmitter::WriteMemory64(const IR::Value& vaddr, const IR::Value& value) {
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void IREmitter::WriteMemory64(const IR::U32& vaddr, const IR::U64& value) {
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if (current_location.EFlag()) {
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auto v = ByteReverseDual(value);
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Inst(Opcode::A32WriteMemory64, {vaddr, v});
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Inst(Opcode::A32WriteMemory64, vaddr, v);
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} else {
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Inst(Opcode::A32WriteMemory64, {vaddr, value});
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Inst(Opcode::A32WriteMemory64, vaddr, value);
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}
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}
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IR::Value IREmitter::ExclusiveWriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
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return Inst(Opcode::A32ExclusiveWriteMemory8, {vaddr, value});
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IR::U32 IREmitter::ExclusiveWriteMemory8(const IR::U32& vaddr, const IR::U8& value) {
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory8, vaddr, value);
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}
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IR::Value IREmitter::ExclusiveWriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
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IR::U32 IREmitter::ExclusiveWriteMemory16(const IR::U32& vaddr, const IR::U16& value) {
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if (current_location.EFlag()) {
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auto v = ByteReverseHalf(value);
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return Inst(Opcode::A32ExclusiveWriteMemory16, {vaddr, v});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory16, vaddr, v);
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} else {
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return Inst(Opcode::A32ExclusiveWriteMemory16, {vaddr, value});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory16, vaddr, value);
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}
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}
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IR::Value IREmitter::ExclusiveWriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
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IR::U32 IREmitter::ExclusiveWriteMemory32(const IR::U32& vaddr, const IR::U32& value) {
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if (current_location.EFlag()) {
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auto v = ByteReverseWord(value);
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return Inst(Opcode::A32ExclusiveWriteMemory32, {vaddr, v});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory32, vaddr, v);
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} else {
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return Inst(Opcode::A32ExclusiveWriteMemory32, {vaddr, value});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory32, vaddr, value);
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}
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}
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IR::Value IREmitter::ExclusiveWriteMemory64(const IR::Value& vaddr, const IR::Value& value_lo, const IR::Value& value_hi) {
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IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& value_lo, const IR::U32& value_hi) {
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if (current_location.EFlag()) {
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auto vlo = ByteReverseWord(value_lo);
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auto vhi = ByteReverseWord(value_hi);
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return Inst(Opcode::A32ExclusiveWriteMemory64, {vaddr, vlo, vhi});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory64, vaddr, vlo, vhi);
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} else {
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return Inst(Opcode::A32ExclusiveWriteMemory64, {vaddr, value_lo, value_hi});
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return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory64, vaddr, value_lo, value_hi);
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}
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}
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void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRd, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2) {
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void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
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ASSERT(coproc_no <= 15);
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std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
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static_cast<u8>(two ? 1 : 0),
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@ -255,10 +255,10 @@ void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1,
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static_cast<u8>(CRn),
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static_cast<u8>(CRm),
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static_cast<u8>(opc2)};
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Inst(Opcode::A32CoprocInternalOperation, {IR::Value(coproc_info)});
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Inst(Opcode::A32CoprocInternalOperation, IR::Value(coproc_info));
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}
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void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2, const IR::Value& word) {
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void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word) {
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ASSERT(coproc_no <= 15);
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std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
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static_cast<u8>(two ? 1 : 0),
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@ -266,19 +266,19 @@ void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, A32::
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static_cast<u8>(CRn),
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static_cast<u8>(CRm),
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static_cast<u8>(opc2)};
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Inst(Opcode::A32CoprocSendOneWord, {IR::Value(coproc_info), word});
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Inst(Opcode::A32CoprocSendOneWord, IR::Value(coproc_info), word);
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}
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void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm, const IR::Value& word1, const IR::Value& word2) {
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void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2) {
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ASSERT(coproc_no <= 15);
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std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
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static_cast<u8>(two ? 1 : 0),
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static_cast<u8>(opc),
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static_cast<u8>(CRm)};
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Inst(Opcode::A32CoprocSendTwoWords, {IR::Value(coproc_info), word1, word2});
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Inst(Opcode::A32CoprocSendTwoWords, IR::Value(coproc_info), word1, word2);
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}
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IR::Value IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2) {
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IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
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ASSERT(coproc_no <= 15);
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std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
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static_cast<u8>(two ? 1 : 0),
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@ -286,19 +286,19 @@ IR::Value IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, A
|
|||
static_cast<u8>(CRn),
|
||||
static_cast<u8>(CRm),
|
||||
static_cast<u8>(opc2)};
|
||||
return Inst(Opcode::A32CoprocGetOneWord, {IR::Value(coproc_info)});
|
||||
return Inst<IR::U32>(Opcode::A32CoprocGetOneWord, IR::Value(coproc_info));
|
||||
}
|
||||
|
||||
IR::Value IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm) {
|
||||
IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
static_cast<u8>(opc),
|
||||
static_cast<u8>(CRm)};
|
||||
return Inst(Opcode::A32CoprocGetTwoWords, {IR::Value(coproc_info)});
|
||||
return Inst<IR::U64>(Opcode::A32CoprocGetTwoWords, IR::Value(coproc_info));
|
||||
}
|
||||
|
||||
void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option) {
|
||||
void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -306,10 +306,10 @@ void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer,
|
|||
static_cast<u8>(CRd),
|
||||
static_cast<u8>(has_option ? 1 : 0),
|
||||
static_cast<u8>(option)};
|
||||
Inst(Opcode::A32CoprocLoadWords, {IR::Value(coproc_info), address});
|
||||
Inst(Opcode::A32CoprocLoadWords, IR::Value(coproc_info), address);
|
||||
}
|
||||
|
||||
void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option) {
|
||||
void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -317,7 +317,7 @@ void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer,
|
|||
static_cast<u8>(CRd),
|
||||
static_cast<u8>(has_option ? 1 : 0),
|
||||
static_cast<u8>(option)};
|
||||
Inst(Opcode::A32CoprocStoreWords, {IR::Value(coproc_info), address});
|
||||
Inst(Opcode::A32CoprocStoreWords, IR::Value(coproc_info), address);
|
||||
}
|
||||
|
||||
} // namespace IR
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue