mirror of
https://git.suyu.dev/suyu/dynarmic.git
synced 2026-01-04 13:44:31 +01:00
IR: Compile-time type-checking of IR
This commit is contained in:
MerryMage
parent
44f7f04b5c
commit
f61da0b5a9
13 changed files with 697 additions and 618 deletions
|
|
@ -23,230 +23,230 @@ u32 IREmitter::AlignPC(size_t alignment) {
|
|||
return static_cast<u32>(pc - pc % alignment);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetRegister(A32::Reg reg) {
|
||||
IR::U32 IREmitter::GetRegister(Reg reg) {
|
||||
if (reg == A32::Reg::PC) {
|
||||
return Imm32(PC());
|
||||
}
|
||||
return Inst(Opcode::A32GetRegister, { IR::Value(reg) });
|
||||
return Inst<IR::U32>(Opcode::A32GetRegister, IR::Value(reg));
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetExtendedRegister(A32::ExtReg reg) {
|
||||
IR::F32F64 IREmitter::GetExtendedRegister(ExtReg reg) {
|
||||
if (A32::IsSingleExtReg(reg)) {
|
||||
return Inst(Opcode::A32GetExtendedRegister32, {IR::Value(reg)});
|
||||
return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
|
||||
}
|
||||
|
||||
if (A32::IsDoubleExtReg(reg)) {
|
||||
return Inst(Opcode::A32GetExtendedRegister64, {IR::Value(reg)});
|
||||
return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
|
||||
}
|
||||
|
||||
ASSERT_MSG(false, "Invalid reg.");
|
||||
}
|
||||
|
||||
void IREmitter::SetRegister(const A32::Reg reg, const IR::Value& value) {
|
||||
void IREmitter::SetRegister(const Reg reg, const IR::U32& value) {
|
||||
ASSERT(reg != A32::Reg::PC);
|
||||
Inst(Opcode::A32SetRegister, { IR::Value(reg), value });
|
||||
Inst(Opcode::A32SetRegister, IR::Value(reg), value);
|
||||
}
|
||||
|
||||
void IREmitter::SetExtendedRegister(const A32::ExtReg reg, const IR::Value& value) {
|
||||
void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::F32F64& value) {
|
||||
if (A32::IsSingleExtReg(reg)) {
|
||||
Inst(Opcode::A32SetExtendedRegister32, {IR::Value(reg), value});
|
||||
Inst(Opcode::A32SetExtendedRegister32, IR::Value(reg), value);
|
||||
} else if (A32::IsDoubleExtReg(reg)) {
|
||||
Inst(Opcode::A32SetExtendedRegister64, {IR::Value(reg), value});
|
||||
Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
|
||||
} else {
|
||||
ASSERT_MSG(false, "Invalid reg.");
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::ALUWritePC(const IR::Value& value) {
|
||||
void IREmitter::ALUWritePC(const IR::U32& value) {
|
||||
// This behaviour is ARM version-dependent.
|
||||
// The below implementation is for ARMv6k
|
||||
BranchWritePC(value);
|
||||
}
|
||||
|
||||
void IREmitter::BranchWritePC(const IR::Value& value) {
|
||||
void IREmitter::BranchWritePC(const IR::U32& value) {
|
||||
if (!current_location.TFlag()) {
|
||||
auto new_pc = And(value, Imm32(0xFFFFFFFC));
|
||||
Inst(Opcode::A32SetRegister, { IR::Value(A32::Reg::PC), new_pc });
|
||||
Inst(Opcode::A32SetRegister, IR::Value(A32::Reg::PC), new_pc);
|
||||
} else {
|
||||
auto new_pc = And(value, Imm32(0xFFFFFFFE));
|
||||
Inst(Opcode::A32SetRegister, { IR::Value(A32::Reg::PC), new_pc });
|
||||
Inst(Opcode::A32SetRegister, IR::Value(A32::Reg::PC), new_pc);
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::BXWritePC(const IR::Value& value) {
|
||||
Inst(Opcode::A32BXWritePC, {value});
|
||||
void IREmitter::BXWritePC(const IR::U32& value) {
|
||||
Inst(Opcode::A32BXWritePC, value);
|
||||
}
|
||||
|
||||
void IREmitter::LoadWritePC(const IR::Value& value) {
|
||||
void IREmitter::LoadWritePC(const IR::U32& value) {
|
||||
// This behaviour is ARM version-dependent.
|
||||
// The below implementation is for ARMv6k
|
||||
BXWritePC(value);
|
||||
}
|
||||
|
||||
void IREmitter::CallSupervisor(const IR::Value& value) {
|
||||
Inst(Opcode::A32CallSupervisor, {value});
|
||||
void IREmitter::CallSupervisor(const IR::U32& value) {
|
||||
Inst(Opcode::A32CallSupervisor, value);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetCpsr() {
|
||||
return Inst(Opcode::A32GetCpsr, {});
|
||||
IR::U32 IREmitter::GetCpsr() {
|
||||
return Inst<IR::U32>(Opcode::A32GetCpsr);
|
||||
}
|
||||
|
||||
void IREmitter::SetCpsr(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetCpsr, {value});
|
||||
void IREmitter::SetCpsr(const IR::U32& value) {
|
||||
Inst(Opcode::A32SetCpsr, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetCpsrNZCV(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetCpsrNZCV, {value});
|
||||
void IREmitter::SetCpsrNZCV(const IR::U32& value) {
|
||||
Inst(Opcode::A32SetCpsrNZCV, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetCpsrNZCVQ(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetCpsrNZCVQ, {value});
|
||||
void IREmitter::SetCpsrNZCVQ(const IR::U32& value) {
|
||||
Inst(Opcode::A32SetCpsrNZCVQ, value);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetCFlag() {
|
||||
return Inst(Opcode::A32GetCFlag, {});
|
||||
IR::U1 IREmitter::GetCFlag() {
|
||||
return Inst<IR::U1>(Opcode::A32GetCFlag);
|
||||
}
|
||||
|
||||
void IREmitter::SetNFlag(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetNFlag, {value});
|
||||
void IREmitter::SetNFlag(const IR::U1& value) {
|
||||
Inst(Opcode::A32SetNFlag, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetZFlag(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetZFlag, {value});
|
||||
void IREmitter::SetZFlag(const IR::U1& value) {
|
||||
Inst(Opcode::A32SetZFlag, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetCFlag(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetCFlag, {value});
|
||||
void IREmitter::SetCFlag(const IR::U1& value) {
|
||||
Inst(Opcode::A32SetCFlag, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetVFlag(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetVFlag, {value});
|
||||
void IREmitter::SetVFlag(const IR::U1& value) {
|
||||
Inst(Opcode::A32SetVFlag, value);
|
||||
}
|
||||
|
||||
void IREmitter::OrQFlag(const IR::Value& value) {
|
||||
Inst(Opcode::A32OrQFlag, {value});
|
||||
void IREmitter::OrQFlag(const IR::U1& value) {
|
||||
Inst(Opcode::A32OrQFlag, value);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetGEFlags() {
|
||||
return Inst(Opcode::A32GetGEFlags, {});
|
||||
IR::U32 IREmitter::GetGEFlags() {
|
||||
return Inst<IR::U32>(Opcode::A32GetGEFlags);
|
||||
}
|
||||
|
||||
void IREmitter::SetGEFlags(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetGEFlags, {value});
|
||||
void IREmitter::SetGEFlags(const IR::U32& value) {
|
||||
Inst(Opcode::A32SetGEFlags, value);
|
||||
}
|
||||
|
||||
void IREmitter::SetGEFlagsCompressed(const IR::Value& value) {
|
||||
Inst(Opcode::A32SetGEFlagsCompressed, {value});
|
||||
void IREmitter::SetGEFlagsCompressed(const IR::U32& value) {
|
||||
Inst(Opcode::A32SetGEFlagsCompressed, value);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetFpscr() {
|
||||
return Inst(Opcode::A32GetFpscr, {});
|
||||
IR::U32 IREmitter::GetFpscr() {
|
||||
return Inst<IR::U32>(Opcode::A32GetFpscr);
|
||||
}
|
||||
|
||||
void IREmitter::SetFpscr(const IR::Value& new_fpscr) {
|
||||
Inst(Opcode::A32SetFpscr, {new_fpscr});
|
||||
void IREmitter::SetFpscr(const IR::U32& new_fpscr) {
|
||||
Inst(Opcode::A32SetFpscr, new_fpscr);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::GetFpscrNZCV() {
|
||||
return Inst(Opcode::A32GetFpscrNZCV, {});
|
||||
IR::U32 IREmitter::GetFpscrNZCV() {
|
||||
return Inst<IR::U32>(Opcode::A32GetFpscrNZCV);
|
||||
}
|
||||
|
||||
void IREmitter::SetFpscrNZCV(const IR::Value& new_fpscr_nzcv) {
|
||||
Inst(Opcode::A32SetFpscrNZCV, {new_fpscr_nzcv});
|
||||
void IREmitter::SetFpscrNZCV(const IR::U32& new_fpscr_nzcv) {
|
||||
Inst(Opcode::A32SetFpscrNZCV, new_fpscr_nzcv);
|
||||
}
|
||||
|
||||
void IREmitter::ClearExclusive() {
|
||||
Inst(Opcode::A32ClearExclusive, {});
|
||||
Inst(Opcode::A32ClearExclusive);
|
||||
}
|
||||
|
||||
void IREmitter::SetExclusive(const IR::Value& vaddr, size_t byte_size) {
|
||||
void IREmitter::SetExclusive(const IR::U32& vaddr, size_t byte_size) {
|
||||
ASSERT(byte_size == 1 || byte_size == 2 || byte_size == 4 || byte_size == 8 || byte_size == 16);
|
||||
Inst(Opcode::A32SetExclusive, {vaddr, Imm8(u8(byte_size))});
|
||||
Inst(Opcode::A32SetExclusive, vaddr, Imm8(u8(byte_size)));
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) {
|
||||
return Inst(Opcode::A32ReadMemory8, {vaddr});
|
||||
IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr) {
|
||||
return Inst<IR::U8>(Opcode::A32ReadMemory8, vaddr);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ReadMemory16(const IR::Value& vaddr) {
|
||||
auto value = Inst(Opcode::A32ReadMemory16, {vaddr});
|
||||
IR::U16 IREmitter::ReadMemory16(const IR::U32& vaddr) {
|
||||
auto value = Inst<IR::U16>(Opcode::A32ReadMemory16, vaddr);
|
||||
return current_location.EFlag() ? ByteReverseHalf(value) : value;
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ReadMemory32(const IR::Value& vaddr) {
|
||||
auto value = Inst(Opcode::A32ReadMemory32, {vaddr});
|
||||
IR::U32 IREmitter::ReadMemory32(const IR::U32& vaddr) {
|
||||
auto value = Inst<IR::U32>(Opcode::A32ReadMemory32, vaddr);
|
||||
return current_location.EFlag() ? ByteReverseWord(value) : value;
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ReadMemory64(const IR::Value& vaddr) {
|
||||
auto value = Inst(Opcode::A32ReadMemory64, {vaddr});
|
||||
IR::U64 IREmitter::ReadMemory64(const IR::U32& vaddr) {
|
||||
auto value = Inst<IR::U64>(Opcode::A32ReadMemory64, vaddr);
|
||||
return current_location.EFlag() ? ByteReverseDual(value) : value;
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
|
||||
Inst(Opcode::A32WriteMemory8, {vaddr, value});
|
||||
void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value) {
|
||||
Inst(Opcode::A32WriteMemory8, vaddr, value);
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
|
||||
void IREmitter::WriteMemory16(const IR::U32& vaddr, const IR::U16& value) {
|
||||
if (current_location.EFlag()) {
|
||||
auto v = ByteReverseHalf(value);
|
||||
Inst(Opcode::A32WriteMemory16, {vaddr, v});
|
||||
Inst(Opcode::A32WriteMemory16, vaddr, v);
|
||||
} else {
|
||||
Inst(Opcode::A32WriteMemory16, {vaddr, value});
|
||||
Inst(Opcode::A32WriteMemory16, vaddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
|
||||
void IREmitter::WriteMemory32(const IR::U32& vaddr, const IR::U32& value) {
|
||||
if (current_location.EFlag()) {
|
||||
auto v = ByteReverseWord(value);
|
||||
Inst(Opcode::A32WriteMemory32, {vaddr, v});
|
||||
Inst(Opcode::A32WriteMemory32, vaddr, v);
|
||||
} else {
|
||||
Inst(Opcode::A32WriteMemory32, {vaddr, value});
|
||||
Inst(Opcode::A32WriteMemory32, vaddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::WriteMemory64(const IR::Value& vaddr, const IR::Value& value) {
|
||||
void IREmitter::WriteMemory64(const IR::U32& vaddr, const IR::U64& value) {
|
||||
if (current_location.EFlag()) {
|
||||
auto v = ByteReverseDual(value);
|
||||
Inst(Opcode::A32WriteMemory64, {vaddr, v});
|
||||
Inst(Opcode::A32WriteMemory64, vaddr, v);
|
||||
} else {
|
||||
Inst(Opcode::A32WriteMemory64, {vaddr, value});
|
||||
Inst(Opcode::A32WriteMemory64, vaddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ExclusiveWriteMemory8(const IR::Value& vaddr, const IR::Value& value) {
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory8, {vaddr, value});
|
||||
IR::U32 IREmitter::ExclusiveWriteMemory8(const IR::U32& vaddr, const IR::U8& value) {
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory8, vaddr, value);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ExclusiveWriteMemory16(const IR::Value& vaddr, const IR::Value& value) {
|
||||
IR::U32 IREmitter::ExclusiveWriteMemory16(const IR::U32& vaddr, const IR::U16& value) {
|
||||
if (current_location.EFlag()) {
|
||||
auto v = ByteReverseHalf(value);
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory16, {vaddr, v});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory16, vaddr, v);
|
||||
} else {
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory16, {vaddr, value});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory16, vaddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ExclusiveWriteMemory32(const IR::Value& vaddr, const IR::Value& value) {
|
||||
IR::U32 IREmitter::ExclusiveWriteMemory32(const IR::U32& vaddr, const IR::U32& value) {
|
||||
if (current_location.EFlag()) {
|
||||
auto v = ByteReverseWord(value);
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory32, {vaddr, v});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory32, vaddr, v);
|
||||
} else {
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory32, {vaddr, value});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory32, vaddr, value);
|
||||
}
|
||||
}
|
||||
|
||||
IR::Value IREmitter::ExclusiveWriteMemory64(const IR::Value& vaddr, const IR::Value& value_lo, const IR::Value& value_hi) {
|
||||
IR::U32 IREmitter::ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& value_lo, const IR::U32& value_hi) {
|
||||
if (current_location.EFlag()) {
|
||||
auto vlo = ByteReverseWord(value_lo);
|
||||
auto vhi = ByteReverseWord(value_hi);
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory64, {vaddr, vlo, vhi});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory64, vaddr, vlo, vhi);
|
||||
} else {
|
||||
return Inst(Opcode::A32ExclusiveWriteMemory64, {vaddr, value_lo, value_hi});
|
||||
return Inst<IR::U32>(Opcode::A32ExclusiveWriteMemory64, vaddr, value_lo, value_hi);
|
||||
}
|
||||
}
|
||||
|
||||
void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRd, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2) {
|
||||
void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -255,10 +255,10 @@ void IREmitter::CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1,
|
|||
static_cast<u8>(CRn),
|
||||
static_cast<u8>(CRm),
|
||||
static_cast<u8>(opc2)};
|
||||
Inst(Opcode::A32CoprocInternalOperation, {IR::Value(coproc_info)});
|
||||
Inst(Opcode::A32CoprocInternalOperation, IR::Value(coproc_info));
|
||||
}
|
||||
|
||||
void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2, const IR::Value& word) {
|
||||
void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -266,19 +266,19 @@ void IREmitter::CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, A32::
|
|||
static_cast<u8>(CRn),
|
||||
static_cast<u8>(CRm),
|
||||
static_cast<u8>(opc2)};
|
||||
Inst(Opcode::A32CoprocSendOneWord, {IR::Value(coproc_info), word});
|
||||
Inst(Opcode::A32CoprocSendOneWord, IR::Value(coproc_info), word);
|
||||
}
|
||||
|
||||
void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm, const IR::Value& word1, const IR::Value& word2) {
|
||||
void IREmitter::CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
static_cast<u8>(opc),
|
||||
static_cast<u8>(CRm)};
|
||||
Inst(Opcode::A32CoprocSendTwoWords, {IR::Value(coproc_info), word1, word2});
|
||||
Inst(Opcode::A32CoprocSendTwoWords, IR::Value(coproc_info), word1, word2);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2) {
|
||||
IR::U32 IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -286,19 +286,19 @@ IR::Value IREmitter::CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, A
|
|||
static_cast<u8>(CRn),
|
||||
static_cast<u8>(CRm),
|
||||
static_cast<u8>(opc2)};
|
||||
return Inst(Opcode::A32CoprocGetOneWord, {IR::Value(coproc_info)});
|
||||
return Inst<IR::U32>(Opcode::A32CoprocGetOneWord, IR::Value(coproc_info));
|
||||
}
|
||||
|
||||
IR::Value IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm) {
|
||||
IR::U64 IREmitter::CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
static_cast<u8>(opc),
|
||||
static_cast<u8>(CRm)};
|
||||
return Inst(Opcode::A32CoprocGetTwoWords, {IR::Value(coproc_info)});
|
||||
return Inst<IR::U64>(Opcode::A32CoprocGetTwoWords, IR::Value(coproc_info));
|
||||
}
|
||||
|
||||
void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option) {
|
||||
void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -306,10 +306,10 @@ void IREmitter::CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer,
|
|||
static_cast<u8>(CRd),
|
||||
static_cast<u8>(has_option ? 1 : 0),
|
||||
static_cast<u8>(option)};
|
||||
Inst(Opcode::A32CoprocLoadWords, {IR::Value(coproc_info), address});
|
||||
Inst(Opcode::A32CoprocLoadWords, IR::Value(coproc_info), address);
|
||||
}
|
||||
|
||||
void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option) {
|
||||
void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option) {
|
||||
ASSERT(coproc_no <= 15);
|
||||
std::array<u8, 8> coproc_info{static_cast<u8>(coproc_no),
|
||||
static_cast<u8>(two ? 1 : 0),
|
||||
|
|
@ -317,7 +317,7 @@ void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer,
|
|||
static_cast<u8>(CRd),
|
||||
static_cast<u8>(has_option ? 1 : 0),
|
||||
static_cast<u8>(option)};
|
||||
Inst(Opcode::A32CoprocStoreWords, {IR::Value(coproc_info), address});
|
||||
Inst(Opcode::A32CoprocStoreWords, IR::Value(coproc_info), address);
|
||||
}
|
||||
|
||||
} // namespace IR
|
||||
|
|
|
|||
|
|
@ -26,65 +26,65 @@ namespace A32 {
|
|||
*/
|
||||
class IREmitter : public IR::IREmitter {
|
||||
public:
|
||||
explicit IREmitter(A32::LocationDescriptor descriptor) : IR::IREmitter(descriptor), current_location(descriptor) {}
|
||||
explicit IREmitter(LocationDescriptor descriptor) : IR::IREmitter(descriptor), current_location(descriptor) {}
|
||||
|
||||
A32::LocationDescriptor current_location;
|
||||
LocationDescriptor current_location;
|
||||
|
||||
u32 PC();
|
||||
u32 AlignPC(size_t alignment);
|
||||
|
||||
IR::Value GetRegister(A32::Reg source_reg);
|
||||
IR::Value GetExtendedRegister(A32::ExtReg source_reg);
|
||||
void SetRegister(const A32::Reg dest_reg, const IR::Value& value);
|
||||
void SetExtendedRegister(const A32::ExtReg dest_reg, const IR::Value& value);
|
||||
IR::U32 GetRegister(Reg source_reg);
|
||||
IR::F32F64 GetExtendedRegister(ExtReg source_reg);
|
||||
void SetRegister(const Reg dest_reg, const IR::U32& value);
|
||||
void SetExtendedRegister(const ExtReg dest_reg, const IR::F32F64& value);
|
||||
|
||||
void ALUWritePC(const IR::Value& value);
|
||||
void BranchWritePC(const IR::Value& value);
|
||||
void BXWritePC(const IR::Value& value);
|
||||
void LoadWritePC(const IR::Value& value);
|
||||
void CallSupervisor(const IR::Value& value);
|
||||
void ALUWritePC(const IR::U32& value);
|
||||
void BranchWritePC(const IR::U32& value);
|
||||
void BXWritePC(const IR::U32& value);
|
||||
void LoadWritePC(const IR::U32& value);
|
||||
void CallSupervisor(const IR::U32& value);
|
||||
|
||||
IR::Value GetCpsr();
|
||||
void SetCpsr(const IR::Value& value);
|
||||
void SetCpsrNZCV(const IR::Value& value);
|
||||
void SetCpsrNZCVQ(const IR::Value& value);
|
||||
IR::Value GetCFlag();
|
||||
void SetNFlag(const IR::Value& value);
|
||||
void SetZFlag(const IR::Value& value);
|
||||
void SetCFlag(const IR::Value& value);
|
||||
void SetVFlag(const IR::Value& value);
|
||||
void OrQFlag(const IR::Value& value);
|
||||
IR::Value GetGEFlags();
|
||||
void SetGEFlags(const IR::Value& value);
|
||||
void SetGEFlagsCompressed(const IR::Value& value);
|
||||
IR::U32 GetCpsr();
|
||||
void SetCpsr(const IR::U32& value);
|
||||
void SetCpsrNZCV(const IR::U32& value);
|
||||
void SetCpsrNZCVQ(const IR::U32& value);
|
||||
IR::U1 GetCFlag();
|
||||
void SetNFlag(const IR::U1& value);
|
||||
void SetZFlag(const IR::U1& value);
|
||||
void SetCFlag(const IR::U1& value);
|
||||
void SetVFlag(const IR::U1& value);
|
||||
void OrQFlag(const IR::U1& value);
|
||||
IR::U32 GetGEFlags();
|
||||
void SetGEFlags(const IR::U32& value);
|
||||
void SetGEFlagsCompressed(const IR::U32& value);
|
||||
|
||||
IR::Value GetFpscr();
|
||||
void SetFpscr(const IR::Value& new_fpscr);
|
||||
IR::Value GetFpscrNZCV();
|
||||
void SetFpscrNZCV(const IR::Value& new_fpscr_nzcv);
|
||||
IR::U32 GetFpscr();
|
||||
void SetFpscr(const IR::U32& new_fpscr);
|
||||
IR::U32 GetFpscrNZCV();
|
||||
void SetFpscrNZCV(const IR::U32& new_fpscr_nzcv);
|
||||
|
||||
void ClearExclusive();
|
||||
void SetExclusive(const IR::Value& vaddr, size_t byte_size);
|
||||
IR::Value ReadMemory8(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory16(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory32(const IR::Value& vaddr);
|
||||
IR::Value ReadMemory64(const IR::Value& vaddr);
|
||||
void WriteMemory8(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory16(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory32(const IR::Value& vaddr, const IR::Value& value);
|
||||
void WriteMemory64(const IR::Value& vaddr, const IR::Value& value);
|
||||
IR::Value ExclusiveWriteMemory8(const IR::Value& vaddr, const IR::Value& value);
|
||||
IR::Value ExclusiveWriteMemory16(const IR::Value& vaddr, const IR::Value& value);
|
||||
IR::Value ExclusiveWriteMemory32(const IR::Value& vaddr, const IR::Value& value);
|
||||
IR::Value ExclusiveWriteMemory64(const IR::Value& vaddr, const IR::Value& value_lo, const IR::Value& value_hi);
|
||||
void SetExclusive(const IR::U32& vaddr, size_t byte_size);
|
||||
IR::U8 ReadMemory8(const IR::U32& vaddr);
|
||||
IR::U16 ReadMemory16(const IR::U32& vaddr);
|
||||
IR::U32 ReadMemory32(const IR::U32& vaddr);
|
||||
IR::U64 ReadMemory64(const IR::U32& vaddr);
|
||||
void WriteMemory8(const IR::U32& vaddr, const IR::U8& value);
|
||||
void WriteMemory16(const IR::U32& vaddr, const IR::U16& value);
|
||||
void WriteMemory32(const IR::U32& vaddr, const IR::U32& value);
|
||||
void WriteMemory64(const IR::U32& vaddr, const IR::U64& value);
|
||||
IR::U32 ExclusiveWriteMemory8(const IR::U32& vaddr, const IR::U8& value);
|
||||
IR::U32 ExclusiveWriteMemory16(const IR::U32& vaddr, const IR::U16& value);
|
||||
IR::U32 ExclusiveWriteMemory32(const IR::U32& vaddr, const IR::U32& value);
|
||||
IR::U32 ExclusiveWriteMemory64(const IR::U32& vaddr, const IR::U32& value_lo, const IR::U32& value_hi);
|
||||
|
||||
void CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRd, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2);
|
||||
void CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2, const IR::Value& word);
|
||||
void CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm, const IR::Value& word1, const IR::Value& word2);
|
||||
IR::Value CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, A32::CoprocReg CRn, A32::CoprocReg CRm, size_t opc2);
|
||||
IR::Value CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, A32::CoprocReg CRm);
|
||||
void CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option);
|
||||
void CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, A32::CoprocReg CRd, const IR::Value& address, bool has_option, u8 option);
|
||||
void CoprocInternalOperation(size_t coproc_no, bool two, size_t opc1, CoprocReg CRd, CoprocReg CRn, CoprocReg CRm, size_t opc2);
|
||||
void CoprocSendOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2, const IR::U32& word);
|
||||
void CoprocSendTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm, const IR::U32& word1, const IR::U32& word2);
|
||||
IR::U32 CoprocGetOneWord(size_t coproc_no, bool two, size_t opc1, CoprocReg CRn, CoprocReg CRm, size_t opc2);
|
||||
IR::U64 CoprocGetTwoWords(size_t coproc_no, bool two, size_t opc, CoprocReg CRm);
|
||||
void CoprocLoadWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option);
|
||||
void CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option);
|
||||
};
|
||||
|
||||
} // namespace IR
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ bool ArmTranslatorVisitor::UnpredictableInstruction() {
|
|||
return false;
|
||||
}
|
||||
|
||||
A32::IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in) {
|
||||
IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitImmShift(IR::U32 value, ShiftType type, Imm5 imm5, IR::U1 carry_in) {
|
||||
switch (type) {
|
||||
case ShiftType::LSL:
|
||||
return ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in);
|
||||
|
|
@ -141,7 +141,7 @@ A32::IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value valu
|
|||
return {};
|
||||
}
|
||||
|
||||
A32::IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in) {
|
||||
IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in) {
|
||||
switch (type) {
|
||||
case ShiftType::LSL:
|
||||
return ir.LogicalShiftLeft(value, amount, carry_in);
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
namespace Dynarmic {
|
||||
namespace A32 {
|
||||
|
||||
static IR::Value Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) {
|
||||
static IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) {
|
||||
const u8 rotate_by = static_cast<u8>(static_cast<size_t>(rotate) * 8);
|
||||
return ir.RotateRight(ir.GetRegister(m), ir.Imm8(rotate_by), ir.Imm1(0)).result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ bool ArmTranslatorVisitor::arm_STRT() {
|
|||
ASSERT_MSG(false, "System instructions unimplemented");
|
||||
}
|
||||
|
||||
static IR::Value GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::Value offset) {
|
||||
static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::U32 offset) {
|
||||
const bool index = P;
|
||||
const bool add = U;
|
||||
const bool wback = !P || W;
|
||||
|
|
@ -608,7 +608,7 @@ bool ArmTranslatorVisitor::arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::Value start_address, IR::Value writeback_address) {
|
||||
static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
|
||||
auto address = start_address;
|
||||
for (size_t i = 0; i <= 14; i++) {
|
||||
if (Common::Bit(i, list)) {
|
||||
|
|
@ -686,7 +686,7 @@ bool ArmTranslatorVisitor::arm_LDM_eret() {
|
|||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::Value start_address, IR::Value writeback_address) {
|
||||
static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
|
||||
auto address = start_address;
|
||||
for (size_t i = 0; i <= 14; i++) {
|
||||
if (Common::Bit(i, list)) {
|
||||
|
|
|
|||
|
|
@ -211,8 +211,7 @@ bool ArmTranslatorVisitor::arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Re
|
|||
auto m32 = ir.GetRegister(m);
|
||||
if (M)
|
||||
m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
|
||||
auto m16 = ir.LeastSignificantHalf(m32);
|
||||
m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
|
||||
auto m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
|
||||
auto product = ir.LeastSignificantWord(ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16)));
|
||||
auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
|
||||
ir.SetRegister(d, result_overflow.result);
|
||||
|
|
@ -229,8 +228,7 @@ bool ArmTranslatorVisitor::arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
|||
auto m32 = ir.GetRegister(m);
|
||||
if (M)
|
||||
m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
|
||||
auto m16 = ir.LeastSignificantHalf(m32);
|
||||
m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
|
||||
auto m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
|
||||
auto result = ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16));
|
||||
ir.SetRegister(d, ir.LeastSignificantWord(result));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,11 +9,11 @@
|
|||
namespace Dynarmic {
|
||||
namespace A32 {
|
||||
|
||||
static IR::Value Pack2x16To1x32(A32::IREmitter& ir, IR::Value lo, IR::Value hi) {
|
||||
static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) {
|
||||
return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result);
|
||||
}
|
||||
|
||||
static IR::Value MostSignificantHalf(A32::IREmitter& ir, IR::Value value) {
|
||||
static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) {
|
||||
return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -49,10 +49,10 @@ struct ArmTranslatorVisitor final {
|
|||
|
||||
struct ImmAndCarry {
|
||||
u32 imm32;
|
||||
IR::Value carry;
|
||||
IR::U1 carry;
|
||||
};
|
||||
|
||||
ImmAndCarry ArmExpandImm_C(int rotate, u32 imm8, IR::Value carry_in) {
|
||||
ImmAndCarry ArmExpandImm_C(int rotate, u32 imm8, IR::U1 carry_in) {
|
||||
u32 imm32 = imm8;
|
||||
auto carry_out = carry_in;
|
||||
if (rotate) {
|
||||
|
|
@ -62,8 +62,8 @@ struct ArmTranslatorVisitor final {
|
|||
return {imm32, carry_out};
|
||||
}
|
||||
|
||||
A32::IREmitter::ResultAndCarry EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in);
|
||||
A32::IREmitter::ResultAndCarry EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in);
|
||||
IR::ResultAndCarry<IR::U32> EmitImmShift(IR::U32 value, ShiftType type, Imm5 imm5, IR::U1 carry_in);
|
||||
IR::ResultAndCarry<IR::U32> EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in);
|
||||
template <typename FnT> bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, ExtReg m, const FnT& fn);
|
||||
template <typename FnT> bool EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg m, const FnT& fn);
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@
|
|||
namespace Dynarmic {
|
||||
namespace A32 {
|
||||
|
||||
using F32 = IR::F32;
|
||||
using F64 = IR::F64;
|
||||
|
||||
static ExtReg ToExtReg(bool sz, size_t base, bool bit) {
|
||||
if (sz) {
|
||||
return static_cast<ExtReg>(static_cast<size_t>(ExtReg::D0) + base + (bit ? 16 : 0));
|
||||
|
|
@ -99,10 +102,13 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
|
||||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPAdd64(reg_n, reg_m, true)
|
||||
: ir.FPAdd32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAdd64(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAdd32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -117,10 +123,13 @@ bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
|
||||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPSub64(reg_n, reg_m, true)
|
||||
: ir.FPSub32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPSub64(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPSub32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -135,10 +144,13 @@ bool ArmTranslatorVisitor::vfp2_VMUL(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
|
||||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPMul64(reg_n, reg_m, true)
|
||||
: ir.FPMul32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPMul64(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPMul32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -154,10 +166,13 @@ bool ArmTranslatorVisitor::vfp2_VMLA(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto reg_d = ir.GetExtendedRegister(d);
|
||||
auto result = sz
|
||||
? ir.FPAdd64(reg_d, ir.FPMul64(reg_n, reg_m, true), true)
|
||||
: ir.FPAdd32(reg_d, ir.FPMul32(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAdd64(reg_d, ir.FPMul64(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAdd32(reg_d, ir.FPMul32(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -173,10 +188,13 @@ bool ArmTranslatorVisitor::vfp2_VMLS(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto reg_d = ir.GetExtendedRegister(d);
|
||||
auto result = sz
|
||||
? ir.FPAdd64(reg_d, ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
|
||||
: ir.FPAdd32(reg_d, ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAdd64(reg_d, ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAdd32(reg_d, ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -191,10 +209,13 @@ bool ArmTranslatorVisitor::vfp2_VNMUL(Cond cond, bool D, size_t Vn, size_t Vd, b
|
|||
return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
|
||||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true))
|
||||
: ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true));
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true));
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true));
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -210,10 +231,13 @@ bool ArmTranslatorVisitor::vfp2_VNMLA(Cond cond, bool D, size_t Vn, size_t Vd, b
|
|||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto reg_d = ir.GetExtendedRegister(d);
|
||||
auto result = sz
|
||||
? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true)
|
||||
: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPNeg64(ir.FPMul64(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPNeg32(ir.FPMul32(reg_n, reg_m, true)), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -229,10 +253,13 @@ bool ArmTranslatorVisitor::vfp2_VNMLS(Cond cond, bool D, size_t Vn, size_t Vd, b
|
|||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto reg_d = ir.GetExtendedRegister(d);
|
||||
auto result = sz
|
||||
? ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPMul64(reg_n, reg_m, true), true)
|
||||
: ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPMul32(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAdd64(ir.FPNeg64(reg_d), ir.FPMul64(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAdd32(ir.FPNeg32(reg_d), ir.FPMul32(reg_n, reg_m, true), true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -247,10 +274,13 @@ bool ArmTranslatorVisitor::vfp2_VDIV(Cond cond, bool D, size_t Vn, size_t Vd, bo
|
|||
return EmitVfpVectorOperation(sz, d, n, m, [sz, this](ExtReg d, ExtReg n, ExtReg m) {
|
||||
auto reg_n = ir.GetExtendedRegister(n);
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPDiv64(reg_n, reg_m, true)
|
||||
: ir.FPDiv32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPDiv64(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPDiv32(reg_n, reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -379,10 +409,13 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool
|
|||
if (ConditionPassed(cond)) {
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPAbs64(reg_m)
|
||||
: ir.FPAbs32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPAbs64(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPAbs32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -395,10 +428,13 @@ bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool
|
|||
if (ConditionPassed(cond)) {
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPNeg64(reg_m)
|
||||
: ir.FPNeg32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPNeg64(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPNeg32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -411,10 +447,13 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
|
|||
if (ConditionPassed(cond)) {
|
||||
return EmitVfpVectorOperation(sz, d, m, [sz, this](ExtReg d, ExtReg m) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPSqrt64(reg_m)
|
||||
: ir.FPSqrt32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPSqrt64(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPSqrt32(reg_m);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
});
|
||||
}
|
||||
return true;
|
||||
|
|
@ -427,10 +466,13 @@ bool ArmTranslatorVisitor::vfp2_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool s
|
|||
// VCVT.F32.F64 <Dd> <Sm>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? ir.FPDoubleToSingle(reg_m, true)
|
||||
: ir.FPSingleToDouble(reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
if (sz) {
|
||||
auto result = ir.FPDoubleToSingle(reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = ir.FPSingleToDouble(reg_m, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -443,14 +485,17 @@ bool ArmTranslatorVisitor::vfp2_VCVT_to_float(Cond cond, bool D, size_t Vd, bool
|
|||
// VCVT.F64.{S32,U32} <Sd>, <Dm>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_m = ir.GetExtendedRegister(m);
|
||||
auto result = sz
|
||||
? is_signed
|
||||
if (sz) {
|
||||
auto result = is_signed
|
||||
? ir.FPS32ToDouble(reg_m, round_to_nearest, true)
|
||||
: ir.FPU32ToDouble(reg_m, round_to_nearest, true)
|
||||
: is_signed
|
||||
: ir.FPU32ToDouble(reg_m, round_to_nearest, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
} else {
|
||||
auto result = is_signed
|
||||
? ir.FPS32ToSingle(reg_m, round_to_nearest, true)
|
||||
: ir.FPU32ToSingle(reg_m, round_to_nearest, true);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
ir.SetExtendedRegister(d, result);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -510,12 +555,11 @@ bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz,
|
|||
// VCMP{E}.F64 <Dd>, #0.0
|
||||
if (ConditionPassed(cond)) {
|
||||
auto reg_d = ir.GetExtendedRegister(d);
|
||||
auto zero = sz
|
||||
? ir.TransferToFP64(ir.Imm64(0))
|
||||
: ir.TransferToFP32(ir.Imm32(0));
|
||||
if (sz) {
|
||||
auto zero = ir.TransferToFP64(ir.Imm64(0));
|
||||
ir.FPCompare64(reg_d, zero, exc_on_qnan, true);
|
||||
} else {
|
||||
auto zero = ir.TransferToFP32(ir.Imm32(0));
|
||||
ir.FPCompare32(reg_d, zero, exc_on_qnan, true);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue