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A64: Implement ISB

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Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
This commit is contained in:
Lioncash 2018-08-17 20:20:42 -04:00 • committed by MerryMage
parent be53e356a2
commit f3f60cd179
9 changed files with 45 additions and 20 deletions
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27
src/frontend/ir/microinstruction.cpp
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@ -395,19 +395,20 @@ bool Inst::IsCoprocessorInstruction() const {
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
op == Opcode::A64InstructionSynchronizationBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction();
}