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A64: Implement FSUB (vector)

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This commit is contained in:
MerryMage 2018-02-11 12:18:05 +00:00
parent b9cd345ddc
commit f1cb5581c9
2 changed files with 15 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -726,7 +726,7 @@ INST(AND_asimd, "AND (vector)", "0Q001
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")
//INST(FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd")
//INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
//INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")