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Fix VShift terminology

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An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
This commit is contained in:
MerryMage 2018-09-23 10:50:39 +01:00
parent b51dae790d
commit f0920c0ded
6 changed files with 170 additions and 170 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -330,7 +330,7 @@ bool TranslatorVisitor::SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(64, Vn);
const IR::U128 operand2 = V(64, Vm);
const IR::U128 result = ir.VectorLogicalVShiftSigned(64, operand1, operand2);
const IR::U128 result = ir.VectorArithmeticVShift(64, operand1, operand2);
V(64, Vd, result);
return true;
@ -361,7 +361,7 @@ bool TranslatorVisitor::USHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(64, Vn);
const IR::U128 operand2 = V(64, Vm);
const IR::U128 result = ir.VectorLogicalVShiftUnsigned(64, operand1, operand2);
const IR::U128 result = ir.VectorLogicalVShift(64, operand1, operand2);
V(64, Vd, result);
return true;

4
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -817,7 +817,7 @@ bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorLogicalVShiftSigned(esize, operand1, operand2);
const IR::U128 result = ir.VectorArithmeticVShift(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
@ -839,7 +839,7 @@ bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorLogicalVShiftUnsigned(esize, operand1, operand2);
const IR::U128 result = ir.VectorLogicalVShift(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}

40
src/frontend/ir/ir_emitter.cpp
View file

@ -888,6 +888,21 @@ U128 IREmitter::VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift
return {};
}
U128 IREmitter::VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorArithmeticVShift8, a, b);
case 16:
return Inst<U128>(Opcode::VectorArithmeticVShift16, a, b);
case 32:
return Inst<U128>(Opcode::VectorArithmeticVShift32, a, b);
case 64:
return Inst<U128>(Opcode::VectorArithmeticVShift64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorBroadcastLower(size_t esize, const UAny& a) {
switch (esize) {
case 8:
@ -1145,31 +1160,16 @@ U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_am
return {};
}
U128 IREmitter::VectorLogicalVShiftSigned(size_t esize, const U128& a, const U128& b) {
U128 IREmitter::VectorLogicalVShift(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorLogicalVShiftS8, a, b);
return Inst<U128>(Opcode::VectorLogicalVShift8, a, b);
case 16:
return Inst<U128>(Opcode::VectorLogicalVShiftS16, a, b);
return Inst<U128>(Opcode::VectorLogicalVShift16, a, b);
case 32:
return Inst<U128>(Opcode::VectorLogicalVShiftS32, a, b);
return Inst<U128>(Opcode::VectorLogicalVShift32, a, b);
case 64:
return Inst<U128>(Opcode::VectorLogicalVShiftS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorLogicalVShiftUnsigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorLogicalVShiftU8, a, b);
case 16:
return Inst<U128>(Opcode::VectorLogicalVShiftU16, a, b);
case 32:
return Inst<U128>(Opcode::VectorLogicalVShiftU32, a, b);
case 64:
return Inst<U128>(Opcode::VectorLogicalVShiftU64, a, b);
return Inst<U128>(Opcode::VectorLogicalVShift64, a, b);
}
UNREACHABLE();
return {};

4
src/frontend/ir/ir_emitter.h
View file

@ -212,6 +212,7 @@ public:
U128 VectorAdd(size_t esize, const U128& a, const U128& b);
U128 VectorAnd(const U128& a, const U128& b);
U128 VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift_amount);
U128 VectorArithmeticVShift(size_t esize, const U128& a, const U128& b);
U128 VectorBroadcast(size_t esize, const UAny& a);
U128 VectorBroadcastLower(size_t esize, const UAny& a);
U128 VectorCountLeadingZeros(size_t esize, const U128& a);
@ -237,8 +238,7 @@ public:
U128 VectorLessUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
U128 VectorLogicalVShiftSigned(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalVShiftUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalVShift(size_t esize, const U128& a, const U128& b);
U128 VectorMaxSigned(size_t esize, const U128& a, const U128& b);
U128 VectorMaxUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorMinSigned(size_t esize, const U128& a, const U128& b);

16
src/frontend/ir/opcodes.inc
View file

@ -253,6 +253,10 @@ OPCODE(VectorArithmeticShiftRight8, U128, U128
OPCODE(VectorArithmeticShiftRight16, U128, U128, U8 )
OPCODE(VectorArithmeticShiftRight32, U128, U128, U8 )
OPCODE(VectorArithmeticShiftRight64, U128, U128, U8 )
OPCODE(VectorArithmeticVShift8, U128, U128, U128 )
OPCODE(VectorArithmeticVShift16, U128, U128, U128 )
OPCODE(VectorArithmeticVShift32, U128, U128, U128 )
OPCODE(VectorArithmeticVShift64, U128, U128, U128 )
OPCODE(VectorBroadcastLower8, U128, U8 )
OPCODE(VectorBroadcastLower16, U128, U16 )
OPCODE(VectorBroadcastLower32, U128, U32 )
@ -311,14 +315,10 @@ OPCODE(VectorLogicalShiftRight8, U128, U128
OPCODE(VectorLogicalShiftRight16, U128, U128, U8 )
OPCODE(VectorLogicalShiftRight32, U128, U128, U8 )
OPCODE(VectorLogicalShiftRight64, U128, U128, U8 )
OPCODE(VectorLogicalVShiftS8, U128, U128, U128 )
OPCODE(VectorLogicalVShiftS16, U128, U128, U128 )
OPCODE(VectorLogicalVShiftS32, U128, U128, U128 )
OPCODE(VectorLogicalVShiftS64, U128, U128, U128 )
OPCODE(VectorLogicalVShiftU8, U128, U128, U128 )
OPCODE(VectorLogicalVShiftU16, U128, U128, U128 )
OPCODE(VectorLogicalVShiftU32, U128, U128, U128 )
OPCODE(VectorLogicalVShiftU64, U128, U128, U128 )
OPCODE(VectorLogicalVShift8, U128, U128, U128 )
OPCODE(VectorLogicalVShift16, U128, U128, U128 )
OPCODE(VectorLogicalVShift32, U128, U128, U128 )
OPCODE(VectorLogicalVShift64, U128, U128, U128 )
OPCODE(VectorMaxS8, U128, U128, U128 )
OPCODE(VectorMaxS16, U128, U128, U128 )
OPCODE(VectorMaxS32, U128, U128, U128 )