Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-05 22:18:16 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

IR: Implement A64OrQC

Browse source
This commit is contained in:
MerryMage 2018-07-24 19:04:40 +01:00
parent f0fecf2615
commit ecbf9dbae5
5 changed files with 22 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/frontend/ir/microinstruction.cpp
View file

@ -341,6 +341,7 @@ bool Inst::ReadsFromFPSRCumulativeSaturationBit() const {
bool Inst::WritesToFPSRCumulativeSaturationBit() const {
switch (op) {
case Opcode::A64OrQC:
case Opcode::VectorSignedSaturatedNarrowToSigned16:
case Opcode::VectorSignedSaturatedNarrowToSigned32:
case Opcode::VectorSignedSaturatedNarrowToSigned64:

1
src/frontend/ir/opcodes.inc
View file

@ -59,6 +59,7 @@ A64OPC(SetQ, T::Void, T::A64Vec,
A64OPC(SetSP, T::Void, T::U64 )
A64OPC(SetFPCR, T::Void, T::U32 )
A64OPC(SetFPSR, T::Void, T::U32 )
A64OPC(OrQC, T::Void, T::U1 )
A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )