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A64: Implement SQSHL's vector register variant

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Lioncash 2018-09-15 20:30:29 -04:00 • committed by MerryMage
parent b14eaaec46
commit e8b0f25dff
2 changed files with 17 additions and 1 deletions
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16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -778,6 +778,22 @@ bool TranslatorVisitor::CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Signed);
}