Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-04 05:34:42 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Start implementing Thumb disassembler

Browse source
This commit is contained in:
MerryMage 2016-07-07 21:51:47 +08:00
parent f31b530703
commit e5f6450a24
10 changed files with 160 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/CMakeLists.txt
View file

@ -12,6 +12,7 @@ set(SRCS
common/x64/cpu_detect.cpp
common/x64/emitter.cpp
frontend/disassembler_arm.cpp
frontend/disassembler_thumb.cpp
frontend/ir/ir.cpp
frontend/ir_emitter.cpp
frontend/translate.cpp
@ -39,7 +40,7 @@ set(HEADERS
frontend/decoder/arm.h
frontend/decoder/decoder_detail.h
frontend/decoder/thumb1.h
frontend/disassembler_arm.h
frontend/disassembler.h
frontend/frontend_arm.h
frontend/ir/ir.h
frontend/ir/opcodes.h

6
src/backend_x64/emit_x64.cpp
View file

@ -221,7 +221,7 @@ void EmitX64::EmitMostSignificantBit(IR::Value* value_) {
// TODO: Flag optimization
code->SHL(32, R(result), Imm8(31));
code->SHR(32, R(result), Imm8(31));
}
void EmitX64::EmitIsZero(IR::Value* value_) {
@ -312,11 +312,11 @@ void EmitX64::EmitLogicalShiftRight(IR::Value* value_) {
// TODO: Optimize this.
code->CMP(32, R(shift), Imm8(32));
code->CMP(8, R(shift), Imm8(32));
auto Rs_gt32 = code->J_CC(CC_A);
auto Rs_eq32 = code->J_CC(CC_E);
// if (Rs & 0xFF == 0) goto end;
code->TEST(32, R(shift), R(shift));
code->TEST(8, R(shift), R(shift));
auto Rs_zero = code->J_CC(CC_Z);
// if (Rs & 0xFF < 32) {
code->SHR(32, R(result), R(shift));

2
src/backend_x64/reg_alloc.cpp
View file

@ -101,7 +101,7 @@ Gen::X64Reg RegAlloc::UseRegister(IR::Value* use_value, std::initializer_list<Ho
code->MOV(32, Gen::R(hostloc_to_x64.at(new_location)), SpillToOpArg(current_location));
hostloc_state[new_location] = HostLocState::Use;
hostloc_to_value[new_location] = use_value;
std::swap(hostloc_to_value[new_location], hostloc_to_value[current_location]);
remaining_uses[use_value]--;
} else if (HostLocIsRegister(current_location)) {
ASSERT(hostloc_state[current_location] == HostLocState::Idle);

4
src/frontend/decoder/thumb1.h
View file

@ -77,8 +77,8 @@ static const std::array<Thumb1Matcher<V>, 7> g_thumb1_instruction_table {{
// { INST(&V::thumb1_AND_reg, "AND (reg)", "0100000000mmmddd") },
// { INST(&V::thumb1_EOR_reg, "EOR (reg)", "0100000001mmmddd") },
{ INST(&V::thumb1_LSL_reg, "LSL (reg)", "0100000010mmmddd") },
{ INST(&V::thumb1_LSR_reg, "LSR (reg)", "0100000011sssddd") },
{ INST(&V::thumb1_ASR_reg, "ASR (reg)", "0100000100sssddd") },
{ INST(&V::thumb1_LSR_reg, "LSR (reg)", "0100000011mmmddd") },
{ INST(&V::thumb1_ASR_reg, "ASR (reg)", "0100000100mmmddd") },
//{ INST(&V::thumb1_ADCS_rr, "ADCS (rr)", "0100000101mmmddd") },
//{ INST(&V::thumb1_SBCS_rr, "SBCS (rr)", "0100000110mmmddd") },
//{ INST(&V::thumb1_RORS_rr, "RORS (rr)", "0100000111sssddd") },

1
src/frontend/disassembler_arm.h → src/frontend/disassembler.h
View file

@ -14,6 +14,7 @@ namespace Dynarmic {
namespace Arm {
std::string DisassembleArm(u32 instruction);
std::string DisassembleThumb16(u16 instruction);
} // namespace Arm
} // namespace Dynarmic

141
src/frontend/disassembler_thumb.cpp Normal file
View file

@ -0,0 +1,141 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2016 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include <cstdlib>
#include <string>
#include "common/bit_util.h"
#include "common/string_util.h"
#include "frontend/arm_types.h"
#include "frontend/decoder/thumb1.h"
namespace Dynarmic {
namespace Arm {
class DisassemblerVisitor {
public:
const char* CondStr(Cond cond) {
switch (cond) {
case Cond::EQ:
return "eq";
case Cond::NE:
return "ne";
case Cond::CS:
return "cs";
case Cond::CC:
return "cc";
case Cond::MI:
return "mi";
case Cond::PL:
return "pl";
case Cond::VS:
return "vs";
case Cond::VC:
return "vc";
case Cond::HI:
return "hi";
case Cond::LS:
return "ls";
case Cond::GE:
return "ge";
case Cond::LT:
return "lt";
case Cond::GT:
return "gt";
case Cond::LE:
return "le";
case Cond::AL:
return "";
case Cond::NV:
break;
}
assert(false);
return "<internal error>";
}
template<typename T>
const char* SignStr(T value) {
return value >= 0 ? "+" : "-";
}
const char* RegStr(Reg reg) {
switch (reg) {
case Reg::R0:
return "r0";
case Reg::R1:
return "r1";
case Reg::R2:
return "r2";
case Reg::R3:
return "r3";
case Reg::R4:
return "r4";
case Reg::R5:
return "r5";
case Reg::R6:
return "r6";
case Reg::R7:
return "r7";
case Reg::R8:
return "r8";
case Reg::R9:
return "r9";
case Reg::R10:
return "r10";
case Reg::R11:
return "r11";
case Reg::R12:
return "r12";
case Reg::R13:
return "sp";
case Reg::R14:
return "lr";
case Reg::R15:
return "pc";
case Reg::INVALID_REG:
break;
}
assert(false);
return "<internal error>";
}
std::string thumb1_LSL_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("lsls %s, %s, #%u", RegStr(d), RegStr(m), imm5);
}
std::string thumb1_LSR_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("lsrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
}
std::string thumb1_ASR_imm(Imm5 imm5, Reg m, Reg d) {
return Common::StringFromFormat("asrs %s, %s, #%u", RegStr(d), RegStr(m), imm5);
}
std::string thumb1_LSL_reg(Reg d_n, Reg m) {
return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_LSR_reg(Reg d_n, Reg m) {
return Common::StringFromFormat("lsrs %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_ASR_reg(Reg d_n, Reg m) {
return Common::StringFromFormat("asrs %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_UDF() {
return Common::StringFromFormat("udf");
}
};
std::string DisassembleThumb16(u16 instruction) {
DisassemblerVisitor visitor;
auto decoder = DecodeThumb16<DisassemblerVisitor>(instruction);
return !decoder ? Common::StringFromFormat("UNKNOWN: %x", instruction) : decoder->call(visitor, instruction);
}
} // namespace Arm
} // namespace Dynarmic