Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-05 22:18:16 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes

Browse source
This commit is contained in:
Lioncash 2019-03-23 10:02:51 -04:00 • committed by MerryMage
parent dff5da1063
commit e4c259d69f
5 changed files with 72 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

16
src/frontend/ir/ir_emitter.cpp
View file

@ -1955,14 +1955,30 @@ U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled)
}
}
U16 IREmitter::FPDoubleToHalf(const U64& a, FP::RoundingMode rounding) {
return Inst<U16>(Opcode::FPDoubleToHalf, a, Imm8(static_cast<u8>(rounding)));
}
U32 IREmitter::FPDoubleToSingle(const U64& a, FP::RoundingMode rounding) {
return Inst<U32>(Opcode::FPDoubleToSingle, a, Imm8(static_cast<u8>(rounding)));
}
U64 IREmitter::FPHalfToDouble(const U16& a, FP::RoundingMode rounding) {
return Inst<U64>(Opcode::FPHalfToDouble, a, Imm8(static_cast<u8>(rounding)));
}
U32 IREmitter::FPHalfToSingle(const U16& a, FP::RoundingMode rounding) {
return Inst<U32>(Opcode::FPHalfToSingle, a, Imm8(static_cast<u8>(rounding)));
}
U64 IREmitter::FPSingleToDouble(const U32& a, FP::RoundingMode rounding) {
return Inst<U64>(Opcode::FPSingleToDouble, a, Imm8(static_cast<u8>(rounding)));
}
U16 IREmitter::FPSingleToHalf(const U32& a, FP::RoundingMode rounding) {
return Inst<U16>(Opcode::FPSingleToHalf, a, Imm8(static_cast<u8>(rounding)));
}
U32 IREmitter::FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding) {
ASSERT(fbits <= 32);
const Opcode opcode = a.GetType() == Type::U32 ? Opcode::FPSingleToFixedS32 : Opcode::FPDoubleToFixedS32;

4
src/frontend/ir/ir_emitter.h
View file

@ -312,7 +312,11 @@ public:
U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b);
U32U64 FPSqrt(const U32U64& a);
U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled);
U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding);
U32 FPDoubleToSingle(const U64& a, FP::RoundingMode rounding);
U64 FPHalfToDouble(const U16& a, FP::RoundingMode rounding);
U32 FPHalfToSingle(const U16& a, FP::RoundingMode rounding);
U16 FPSingleToHalf(const U32& a, FP::RoundingMode rounding);
U64 FPSingleToDouble(const U32& a, FP::RoundingMode rounding);
U32 FPToFixedS32(const U32U64& a, size_t fbits, FP::RoundingMode rounding);
U64 FPToFixedS64(const U32U64& a, size_t fbits, FP::RoundingMode rounding);

4
src/frontend/ir/microinstruction.cpp
View file

@ -288,7 +288,11 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPSqrt64:
case Opcode::FPSub32:
case Opcode::FPSub64:
case Opcode::FPHalfToDouble:
case Opcode::FPHalfToSingle:
case Opcode::FPSingleToDouble:
case Opcode::FPSingleToHalf:
case Opcode::FPDoubleToHalf:
case Opcode::FPDoubleToSingle:
case Opcode::FPDoubleToFixedS32:
case Opcode::FPDoubleToFixedS64:

4
src/frontend/ir/opcodes.inc
View file

@ -503,7 +503,11 @@ OPCODE(FPSub32, U32, U32,
OPCODE(FPSub64, U64, U64, U64 )
// Floating-point conversions
OPCODE(FPHalfToDouble, U64, U16, U8 )
OPCODE(FPHalfToSingle, U32, U16, U8 )
OPCODE(FPSingleToDouble, U64, U32, U8 )
OPCODE(FPSingleToHalf, U16, U32, U8 )
OPCODE(FPDoubleToHalf, U16, U64, U8 )
OPCODE(FPDoubleToSingle, U32, U64, U8 )
OPCODE(FPDoubleToFixedS32, U32, U64, U8, U8 )
OPCODE(FPDoubleToFixedS64, U64, U64, U8, U8 )