Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-08 23:48:18 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A64: Implement system registers FPCR and FPSR

Browse source
This commit is contained in:
MerryMage 2018-02-20 17:38:29 +00:00
parent 9e4e4e9c1d
commit e3da92024e
12 changed files with 216 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

20
src/frontend/A64/translate/impl/system.cpp
View file

@ -51,6 +51,20 @@ bool TranslatorVisitor::DMB(Imm<4> /*CRm*/) {
return true;
}
bool TranslatorVisitor::MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
const size_t sys_reg = concatenate(Imm<1>{1}, o0, op1, CRn, CRm, op2).ZeroExtend<size_t>();
switch (sys_reg) {
case 0b11'011'0100'0100'000: // FPCR
ir.SetFPCR(X(32, Rt));
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
case 0b11'011'0100'0100'001: // FPSR
ir.SetFPSR(X(32, Rt));
return true;
}
return InterpretThisInstruction();
}
bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
const size_t sys_reg = concatenate(Imm<1>{1}, o0, op1, CRn, CRm, op2).ZeroExtend<size_t>();
switch (sys_reg) {
@ -66,6 +80,12 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
case 0b11'011'1110'0000'001: // CNTPCT_EL0
X(64, Rt, ir.GetCNTPCT());
return true;
case 0b11'011'0100'0100'000: // FPCR
X(32, Rt, ir.GetFPCR());
return true;
case 0b11'011'0100'0100'001: // FPSR
X(32, Rt, ir.GetFPSR());
return true;
}
return InterpretThisInstruction();
}