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Port x64 backend to xbyak
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MerryMage
parent
611cffb612
commit
e32812cd00
25 changed files with 1638 additions and 5323 deletions
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@ -11,93 +11,55 @@
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#include <vector>
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#include <boost/optional.hpp>
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#include <xbyak.h>
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#include "backend_x64/block_of_code.h"
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#include "backend_x64/hostloc.h"
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#include "backend_x64/jitstate.h"
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#include "common/common_types.h"
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#include "common/x64/emitter.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/value.h"
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namespace Dynarmic {
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namespace BackendX64 {
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enum class HostLoc {
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// Ordering of the registers is intentional. See also: HostLocToX64.
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RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
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CF, PF, AF, ZF, SF, OF,
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FirstSpill,
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};
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struct OpArg {
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OpArg() : type(OPERAND), inner_operand() {}
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OpArg(const Xbyak::Address& address) : type(ADDRESS), inner_address(address) {}
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OpArg(const Xbyak::Operand& operand) : type(OPERAND), inner_operand(operand) {}
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constexpr size_t HostLocCount = static_cast<size_t>(HostLoc::FirstSpill) + SpillCount;
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Xbyak::Operand& operator*() {
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switch (type) {
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case ADDRESS:
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return inner_address;
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case OPERAND:
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return inner_operand;
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}
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ASSERT_MSG(false, "Unreachable");
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}
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enum class HostLocState {
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Idle, Def, Use, Scratch
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};
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void setBit(int bits) {
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switch (type) {
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case ADDRESS:
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inner_address.setBit(bits);
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return;
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case OPERAND:
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inner_operand.setBit(bits);
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return;
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}
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ASSERT_MSG(false, "Unreachable");
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}
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inline bool HostLocIsGPR(HostLoc reg) {
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return reg >= HostLoc::RAX && reg <= HostLoc::R14;
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}
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private:
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enum {
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OPERAND,
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ADDRESS,
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} type;
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inline bool HostLocIsXMM(HostLoc reg) {
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return reg >= HostLoc::XMM0 && reg <= HostLoc::XMM15;
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}
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inline bool HostLocIsRegister(HostLoc reg) {
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return HostLocIsGPR(reg) || HostLocIsXMM(reg);
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}
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inline bool HostLocIsFlag(HostLoc reg) {
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return reg >= HostLoc::CF && reg <= HostLoc::OF;
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}
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inline HostLoc HostLocSpill(size_t i) {
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ASSERT_MSG(i < SpillCount, "Invalid spill");
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return static_cast<HostLoc>(static_cast<int>(HostLoc::FirstSpill) + i);
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}
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inline bool HostLocIsSpill(HostLoc reg) {
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return reg >= HostLoc::FirstSpill && reg <= HostLocSpill(SpillCount - 1);
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}
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using HostLocList = std::initializer_list<HostLoc>;
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const HostLocList any_gpr = {
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HostLoc::RAX,
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HostLoc::RBX,
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HostLoc::RCX,
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HostLoc::RDX,
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HostLoc::RSI,
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HostLoc::RDI,
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HostLoc::RBP,
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HostLoc::R8,
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HostLoc::R9,
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HostLoc::R10,
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HostLoc::R11,
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HostLoc::R12,
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HostLoc::R13,
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HostLoc::R14,
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};
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const HostLocList any_xmm = {
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HostLoc::XMM0,
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HostLoc::XMM1,
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HostLoc::XMM2,
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HostLoc::XMM3,
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HostLoc::XMM4,
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HostLoc::XMM5,
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HostLoc::XMM6,
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HostLoc::XMM7,
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HostLoc::XMM8,
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HostLoc::XMM9,
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HostLoc::XMM10,
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HostLoc::XMM11,
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HostLoc::XMM12,
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HostLoc::XMM13,
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HostLoc::XMM14,
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HostLoc::XMM15,
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union {
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Xbyak::Operand inner_operand;
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Xbyak::Address inner_address;
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};
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};
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class RegAlloc final {
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@ -105,21 +67,54 @@ public:
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RegAlloc(BlockOfCode* code) : code(code) {}
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/// Late-def
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Gen::X64Reg DefRegister(IR::Inst* def_inst, HostLocList desired_locations);
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Xbyak::Reg64 DefGpr(IR::Inst* def_inst, HostLocList desired_locations = any_gpr) {
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return HostLocToReg64(DefHostLocReg(def_inst, desired_locations));
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}
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Xbyak::Xmm DefXmm(IR::Inst* def_inst, HostLocList desired_locations = any_xmm) {
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return HostLocToXmm(DefHostLocReg(def_inst, desired_locations));
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}
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void RegisterAddDef(IR::Inst* def_inst, const IR::Value& use_inst);
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/// Early-use, Late-def
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Gen::X64Reg UseDefRegister(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations);
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Gen::X64Reg UseDefRegister(IR::Inst* use_inst, IR::Inst* def_inst, HostLocList desired_locations);
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std::tuple<Gen::OpArg, Gen::X64Reg> UseDefOpArg(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations);
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Xbyak::Reg64 UseDefGpr(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations = any_gpr) {
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return HostLocToReg64(UseDefHostLocReg(use_value, def_inst, desired_locations));
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}
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Xbyak::Xmm UseDefXmm(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations = any_xmm) {
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return HostLocToXmm(UseDefHostLocReg(use_value, def_inst, desired_locations));
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}
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std::tuple<OpArg, Xbyak::Reg64> UseDefOpArgGpr(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations = any_gpr) {
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OpArg op;
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HostLoc host_loc;
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std::tie(op, host_loc) = UseDefOpArgHostLocReg(use_value, def_inst, desired_locations);
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return std::make_tuple(op, HostLocToReg64(host_loc));
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}
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std::tuple<OpArg, Xbyak::Xmm> UseDefOpArgXmm(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations = any_gpr) {
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OpArg op;
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HostLoc host_loc;
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std::tie(op, host_loc) = UseDefOpArgHostLocReg(use_value, def_inst, desired_locations);
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return std::make_tuple(op, HostLocToXmm(host_loc));
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}
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/// Early-use
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Gen::X64Reg UseRegister(IR::Value use_value, HostLocList desired_locations);
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Gen::X64Reg UseRegister(IR::Inst* use_inst, HostLocList desired_locations);
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Gen::OpArg UseOpArg(IR::Value use_value, HostLocList desired_locations);
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Xbyak::Reg64 UseGpr(IR::Value use_value, HostLocList desired_locations = any_gpr) {
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return HostLocToReg64(UseHostLocReg(use_value, desired_locations));
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}
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Xbyak::Xmm UseXmm(IR::Value use_value, HostLocList desired_locations = any_xmm) {
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return HostLocToXmm(UseHostLocReg(use_value, desired_locations));
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}
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OpArg UseOpArg(IR::Value use_value, HostLocList desired_locations);
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/// Early-use, Destroyed
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Gen::X64Reg UseScratchRegister(IR::Value use_value, HostLocList desired_locations);
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Gen::X64Reg UseScratchRegister(IR::Inst* use_inst, HostLocList desired_locations);
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Xbyak::Reg64 UseScratchGpr(IR::Value use_value, HostLocList desired_locations = any_gpr) {
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return HostLocToReg64(UseScratchHostLocReg(use_value, desired_locations));
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}
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Xbyak::Xmm UseScratchXmm(IR::Value use_value, HostLocList desired_locations = any_xmm) {
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return HostLocToXmm(UseScratchHostLocReg(use_value, desired_locations));
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}
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/// Early-def, Late-use, single-use
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Gen::X64Reg ScratchRegister(HostLocList desired_locations);
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Xbyak::Reg64 ScratchGpr(HostLocList desired_locations = any_gpr) {
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return HostLocToReg64(ScratchHostLocReg(desired_locations));
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}
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Xbyak::Xmm ScratchXmm(HostLocList desired_locations = any_xmm) {
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return HostLocToXmm(ScratchHostLocReg(desired_locations));
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}
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/// Late-def for result register, Early-use for all arguments, Each value is placed into registers according to host ABI.
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void HostCall(IR::Inst* result_def = nullptr, IR::Value arg0_use = {}, IR::Value arg1_use = {}, IR::Value arg2_use = {}, IR::Value arg3_use = {});
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@ -141,11 +136,20 @@ private:
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bool IsRegisterAllocated(HostLoc loc) const;
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bool IsLastUse(IR::Inst* inst) const;
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HostLoc DefHostLocReg(IR::Inst* def_inst, HostLocList desired_locations);
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HostLoc UseDefHostLocReg(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations);
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HostLoc UseDefHostLocReg(IR::Inst* use_inst, IR::Inst* def_inst, HostLocList desired_locations);
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std::tuple<OpArg, HostLoc> UseDefOpArgHostLocReg(IR::Value use_value, IR::Inst* def_inst, HostLocList desired_locations);
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HostLoc UseHostLocReg(IR::Value use_value, HostLocList desired_locations);
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HostLoc UseHostLocReg(IR::Inst* use_inst, HostLocList desired_locations);
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std::tuple<HostLoc, bool> UseHostLoc(IR::Inst* use_inst, HostLocList desired_locations);
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HostLoc UseScratchHostLocReg(IR::Value use_value, HostLocList desired_locations);
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HostLoc UseScratchHostLocReg(IR::Inst* use_inst, HostLocList desired_locations);
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HostLoc ScratchHostLocReg(HostLocList desired_locations);
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void EmitMove(HostLoc to, HostLoc from);
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void EmitExchange(HostLoc a, HostLoc b);
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Gen::X64Reg LoadImmediateIntoRegister(IR::Value imm, Gen::X64Reg reg);
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HostLoc LoadImmediateIntoHostLocReg(IR::Value imm, HostLoc reg);
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void SpillRegister(HostLoc loc);
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HostLoc FindFreeSpill() const;
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