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https://git.suyu.dev/suyu/dynarmic.git
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IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
This commit is contained in:
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e00a522cba
commit
e1df7ae621
9 changed files with 72 additions and 4 deletions
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@ -58,6 +58,10 @@ IR::U64 IREmitter::ReadMemory64(const IR::U64& vaddr) {
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return Inst<IR::U64>(Opcode::A64ReadMemory64, vaddr);
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}
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IR::U128 IREmitter::ReadMemory128(const IR::U64& vaddr) {
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return Inst<IR::U128>(Opcode::A64ReadMemory128, vaddr);
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}
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void IREmitter::WriteMemory8(const IR::U64& vaddr, const IR::U8& value) {
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Inst(Opcode::A64WriteMemory8, vaddr, value);
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}
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@ -74,6 +78,10 @@ void IREmitter::WriteMemory64(const IR::U64& vaddr, const IR::U64& value) {
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Inst(Opcode::A64WriteMemory64, vaddr, value);
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}
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void IREmitter::WriteMemory128(const IR::U64& vaddr, const IR::U128& value) {
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Inst(Opcode::A64WriteMemory128, vaddr, value);
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}
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IR::U32 IREmitter::GetW(Reg reg) {
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if (reg == Reg::ZR)
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return Imm32(0);
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@ -44,10 +44,12 @@ public:
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IR::U16 ReadMemory16(const IR::U64& vaddr);
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IR::U32 ReadMemory32(const IR::U64& vaddr);
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IR::U64 ReadMemory64(const IR::U64& vaddr);
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IR::U128 ReadMemory128(const IR::U64& vaddr);
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void WriteMemory8(const IR::U64& vaddr, const IR::U8& value);
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void WriteMemory16(const IR::U64& vaddr, const IR::U16& value);
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void WriteMemory32(const IR::U64& vaddr, const IR::U32& value);
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void WriteMemory64(const IR::U64& vaddr, const IR::U64& value);
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void WriteMemory128(const IR::U64& vaddr, const IR::U128& value);
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IR::U32 GetW(Reg source_reg);
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IR::U64 GetX(Reg source_reg);
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@ -147,7 +147,7 @@ void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
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}
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}
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IR::UAny TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*/) {
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IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*/) {
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switch (bytesize) {
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case 1:
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return ir.ReadMemory8(address);
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@ -157,13 +157,15 @@ IR::UAny TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acct
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return ir.ReadMemory32(address);
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case 8:
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return ir.ReadMemory64(address);
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case 16:
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return ir.ReadMemory128(address);
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default:
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ASSERT_MSG(false, "Invalid bytesize parameter %zu", bytesize);
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return {};
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}
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}
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void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*/, IR::UAny value) {
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void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*/, IR::UAnyU128 value) {
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switch (bytesize) {
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case 1:
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ir.WriteMemory8(address, value);
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@ -177,6 +179,9 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, AccType /*acctype*
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case 8:
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ir.WriteMemory64(address, value);
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return;
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case 16:
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ir.WriteMemory128(address, value);
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return;
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default:
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ASSERT_MSG(false, "Invalid bytesize parameter %zu", bytesize);
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return;
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@ -51,8 +51,8 @@ struct TranslatorVisitor final {
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IR::U128 V(size_t bitsize, Vec vec);
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void V(size_t bitsize, Vec vec, IR::U128 value);
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IR::UAny Mem(IR::U64 address, size_t size, AccType acctype);
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void Mem(IR::U64 address, size_t size, AccType acctype, IR::UAny value);
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IR::UAnyU128 Mem(IR::U64 address, size_t size, AccType acctype);
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void Mem(IR::U64 address, size_t size, AccType acctype, IR::UAnyU128 value);
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IR::U32U64 SignExtend(IR::UAny value, size_t to_size);
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IR::U32U64 ZeroExtend(IR::UAny value, size_t to_size);
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@ -237,10 +237,12 @@ A64OPC(ReadMemory8, T::U8, T::U64
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A64OPC(ReadMemory16, T::U16, T::U64 )
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A64OPC(ReadMemory32, T::U32, T::U64 )
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A64OPC(ReadMemory64, T::U64, T::U64 )
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A64OPC(ReadMemory128, T::U128, T::U64 )
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A64OPC(WriteMemory8, T::Void, T::U64, T::U8 )
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A64OPC(WriteMemory16, T::Void, T::U64, T::U16 )
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A64OPC(WriteMemory32, T::Void, T::U64, T::U32 )
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A64OPC(WriteMemory64, T::Void, T::U64, T::U64 )
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A64OPC(WriteMemory128, T::Void, T::U64, T::U128 )
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// Coprocessor
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A32OPC(CoprocInternalOperation, T::Void, T::CoprocInfo )
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@ -100,6 +100,7 @@ using U64 = TypedValue<Type::U64>;
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using U128 = TypedValue<Type::U128>;
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using U32U64 = TypedValue<Type::U32 | Type::U64>;
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using UAny = TypedValue<Type::U8 | Type::U16 | Type::U32 | Type::U64>;
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using UAnyU128 = TypedValue<Type::U8 | Type::U16 | Type::U32 | Type::U64 | Type::U128>;
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using NZCV = TypedValue<Type::NZCVFlags>;
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} // namespace IR
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