Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-03 13:14:42 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

TranslateArm: Implement MRS, MSR (imm), MSR (reg)

Browse source
This commit is contained in:
MerryMage 2016-08-14 19:39:16 +01:00
parent 30f3d869cc
commit e164ede4dc
9 changed files with 95 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/backend_x64/emit_x64.cpp
View file

@ -209,6 +209,16 @@ void EmitX64::EmitSetZFlag(IR::Block&, IR::Inst* inst) {
}
}
void EmitX64::EmitGetCpsr(IR::Block&, IR::Inst* inst) {
X64Reg result = reg_alloc.DefRegister(inst, any_gpr);
code->MOV(32, R(result), MJitStateCpsr());
}
void EmitX64::EmitSetCpsr(IR::Block&, IR::Inst* inst) {
X64Reg arg = reg_alloc.UseRegister(inst->GetArg(0), any_gpr);
code->MOV(32, MJitStateCpsr(), R(arg));
}
void EmitX64::EmitGetCFlag(IR::Block&, IR::Inst* inst) {
X64Reg result = reg_alloc.DefRegister(inst, any_gpr);
code->MOV(32, R(result), MJitStateCpsr());