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A32: Implement ASIMD VSUB (floating-point)

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This commit is contained in:
MerryMage 2020-06-20 13:39:03 +01:00
parent 4c939b9d0a
commit e006f0a205
7 changed files with 16 additions and 9 deletions
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6
src/frontend/ir/ir_emitter.cpp
View file

@ -2513,12 +2513,12 @@ U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a) {
UNREACHABLE();
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorSub32, a, b);
return Inst<U128>(Opcode::FPVectorSub32, a, b, Imm1(fpcr_controlled));
case 64:
return Inst<U128>(Opcode::FPVectorSub64, a, b);
return Inst<U128>(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled));
}
UNREACHABLE();
}

2
src/frontend/ir/ir_emitter.h
View file

@ -366,7 +366,7 @@ public:
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSqrt(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);

4
src/frontend/ir/opcodes.inc
View file

@ -630,8 +630,8 @@ OPCODE(FPVectorRSqrtStepFused32, U128, U128
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
OPCODE(FPVectorSqrt32, U128, U128 )
OPCODE(FPVectorSqrt64, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128 )
OPCODE(FPVectorSub64, U128, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128, U1 )
OPCODE(FPVectorSub64, U128, U128, U128, U1 )
OPCODE(FPVectorToSignedFixed16, U128, U128, U8, U8 )
OPCODE(FPVectorToSignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorToSignedFixed64, U128, U128, U8, U8 )