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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB

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This commit is contained in:
MerryMage 2016-08-09 22:48:20 +01:00
parent d921390928
commit df39308e03
12 changed files with 446 additions and 98 deletions
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42
src/ir_opt/dead_code_elimination_pass.cpp
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@ -13,7 +13,47 @@ namespace Optimization {
void DeadCodeElimination(IR::Block& block) {
const auto is_side_effect_free = [](IR::Opcode op) -> bool {
return IR::GetTypeOf(op) != IR::Type::Void;
switch (op) {
case IR::Opcode::Breakpoint:
case IR::Opcode::SetRegister:
case IR::Opcode::SetExtendedRegister32:
case IR::Opcode::SetExtendedRegister64:
case IR::Opcode::SetNFlag:
case IR::Opcode::SetZFlag:
case IR::Opcode::SetCFlag:
case IR::Opcode::SetVFlag:
case IR::Opcode::OrQFlag:
case IR::Opcode::BXWritePC:
case IR::Opcode::CallSupervisor:
case IR::Opcode::FPAbs32:
case IR::Opcode::FPAbs64:
case IR::Opcode::FPAdd32:
case IR::Opcode::FPAdd64:
case IR::Opcode::FPDiv32:
case IR::Opcode::FPDiv64:
case IR::Opcode::FPMul32:
case IR::Opcode::FPMul64:
case IR::Opcode::FPNeg32:
case IR::Opcode::FPNeg64:
case IR::Opcode::FPSqrt32:
case IR::Opcode::FPSqrt64:
case IR::Opcode::FPSub32:
case IR::Opcode::FPSub64:
case IR::Opcode::ClearExclusive:
case IR::Opcode::SetExclusive:
case IR::Opcode::WriteMemory8:
case IR::Opcode::WriteMemory16:
case IR::Opcode::WriteMemory32:
case IR::Opcode::WriteMemory64:
case IR::Opcode::ExclusiveWriteMemory8:
case IR::Opcode::ExclusiveWriteMemory16:
case IR::Opcode::ExclusiveWriteMemory32:
case IR::Opcode::ExclusiveWriteMemory64:
return false;
default:
ASSERT(IR::GetTypeOf(op) != IR::Type::Void);
return true;
}
};
// We iterate over the instructions in reverse order.