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Implemented the ARM SEL instruction, with tests. (#39)
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
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3 changed files with 57 additions and 1 deletions
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@ -904,3 +904,29 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][vfp]") {
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return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
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});
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}
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TEST_CASE("Test ARM SEL instruction", "[JitX64]") {
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const auto is_sel_valid = [](u32 instr) -> bool {
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// R15 as Rd, Rn, or Rm is UNPREDICTABLE
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return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111 && Bits<16, 19>(instr) != 0b1111;
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};
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const auto is_msr_valid = [](u32 instr) -> bool {
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// Mask can not be 0
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return Bits<18, 19>(instr) != 0b00;
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};
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const InstructionGenerator cpsr_setter = InstructionGenerator("11100011001001001111rrrrvvvvvvvv", is_msr_valid); // MSR_Imm write GE
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const InstructionGenerator sel_instr = InstructionGenerator("111001101000nnnndddd11111011mmmm", is_sel_valid); // SEL
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SECTION("Fuzz SEL") {
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// Alternate between a SEL and a MSR to change the CPSR, thus changing the expected result of the next SEL
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bool set_cpsr = true;
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FuzzJitArm(5, 6, 10000, [&sel_instr, &cpsr_setter, &set_cpsr]() -> u32 {
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set_cpsr ^= true;
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if (set_cpsr)
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return cpsr_setter.Generate(false);
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return sel_instr.Generate(false);
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});
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}
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}
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