A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR

This commit is contained in:
MerryMage 2018-02-05 15:41:41 +00:00
parent 81713c2b77
commit cc9efd13c9
3 changed files with 30 additions and 3 deletions

View file

@ -132,9 +132,9 @@ INST(LDx_mult_2, "LDx (multiple structures)", "0Q001
//INST(LDAXRB, "LDAXRB", "zz00100001011111111111nnnnnttttt")
//INST(LDXP, "LDXP", "1z001000011111110uuuuunnnnnttttt")
//INST(LDAXP, "LDAXP", "1z001000011111111uuuuunnnnnttttt")
//INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt")
INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt")
INST(STLR, "STLRB, STLRH, STLR", "zz00100010011111111111nnnnnttttt")
//INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt")
INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt")
INST(LDAR, "LDARB, LDARH, LDAR", "zz00100011011111111111nnnnnttttt")
//INST(CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt") // ARMv8.1
//INST(CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt") // ARMv8.1

View file

@ -47,6 +47,13 @@ static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& tv, size_t size,
return true;
}
bool TranslatorVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) {
const size_t size = sz.ZeroExtend<size_t>();
const bool L = 0;
const bool o0 = 0;
return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
}
bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
const size_t size = sz.ZeroExtend<size_t>();
const bool L = 0;
@ -54,6 +61,13 @@ bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
}
bool TranslatorVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) {
const size_t size = sz.ZeroExtend<size_t>();
const bool L = 1;
const bool o0 = 0;
return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
}
bool TranslatorVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) {
const size_t size = sz.ZeroExtend<size_t>();
const bool L = 1;