mirror of
https://git.suyu.dev/suyu/dynarmic.git
synced 2026-01-04 13:44:31 +01:00
Better MSVC support
* Avoiding use of templated variables. * Now compling on MSVC with /WX (warnings as errors). * Fixed all MSVC warnings. * Fixed MSVC source_groups.
This commit is contained in:
MerryMage
parent
bf99ddd065
commit
c18a3eeab4
17 changed files with 392 additions and 361 deletions
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@ -9,9 +9,8 @@
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#pragma once
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#include <algorithm>
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#include <array>
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#include <functional>
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#include <tuple>
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#include <vector>
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#include <boost/optional.hpp>
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@ -58,293 +57,291 @@ private:
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std::function<CallRetT(Visitor&, u32)> fn;
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};
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template <typename V>
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static const std::array<ArmMatcher<V>, 6> g_arm_instruction_table = {
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template<typename V>
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boost::optional<const ArmMatcher<V>&> DecodeArm(u32 instruction) {
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const static std::vector<ArmMatcher<V>> table = {
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#define INST(fn, name, bitstring) detail::detail<ArmMatcher, u32, 32>::GetMatcher<decltype(fn), fn>(name, bitstring)
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// Branch instructions
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//INST(&V::arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv"), // v5
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//INST(&V::arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm"), // v5
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//INST(&V::arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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//INST(&V::arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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//INST(&V::arm_BX, "BX", "cccc000100101111111111110001mmmm"), // v4T
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//INST(&V::arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm"), // v5J
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// Branch instructions
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//INST(&V::arm_BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv"), // v5
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//INST(&V::arm_BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm"), // v5
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//INST(&V::arm_B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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//INST(&V::arm_BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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//INST(&V::arm_BX, "BX", "cccc000100101111111111110001mmmm"), // v4T
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//INST(&V::arm_BXJ, "BXJ", "cccc000100101111111111110010mmmm"), // v5J
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// Coprocessor instructions
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//INST(&V::arm_CDP, "CDP2", "11111110-------------------1----"), // v5
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//INST(&V::arm_CDP, "CDP", "----1110-------------------0----"), // v2
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//INST(&V::arm_LDC, "LDC2", "1111110----1--------------------"), // v5
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//INST(&V::arm_LDC, "LDC", "----110----1--------------------"), // v2
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//INST(&V::arm_MCR, "MCR2", "----1110---0---------------1----"), // v5
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//INST(&V::arm_MCR, "MCR", "----1110---0---------------1----"), // v2
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//INST(&V::arm_MCRR, "MCRR2", "111111000100--------------------"), // v6
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//INST(&V::arm_MCRR, "MCRR", "----11000100--------------------"), // v5E
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//INST(&V::arm_MRC, "MRC2", "11111110---1---------------1----"), // v5
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//INST(&V::arm_MRC, "MRC", "----1110---1---------------1----"), // v2
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//INST(&V::arm_MRRC, "MRRC2", "111111000101--------------------"), // v6
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//INST(&V::arm_MRRC, "MRRC", "----11000101--------------------"), // v5E
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//INST(&V::arm_STC, "STC2", "1111110----0--------------------"), // v5
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//INST(&V::arm_STC, "STC", "----110----0--------------------"), // v2
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// Coprocessor instructions
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//INST(&V::arm_CDP, "CDP2", "11111110-------------------1----"), // v5
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//INST(&V::arm_CDP, "CDP", "----1110-------------------0----"), // v2
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//INST(&V::arm_LDC, "LDC2", "1111110----1--------------------"), // v5
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//INST(&V::arm_LDC, "LDC", "----110----1--------------------"), // v2
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//INST(&V::arm_MCR, "MCR2", "----1110---0---------------1----"), // v5
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//INST(&V::arm_MCR, "MCR", "----1110---0---------------1----"), // v2
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//INST(&V::arm_MCRR, "MCRR2", "111111000100--------------------"), // v6
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//INST(&V::arm_MCRR, "MCRR", "----11000100--------------------"), // v5E
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//INST(&V::arm_MRC, "MRC2", "11111110---1---------------1----"), // v5
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//INST(&V::arm_MRC, "MRC", "----1110---1---------------1----"), // v2
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//INST(&V::arm_MRRC, "MRRC2", "111111000101--------------------"), // v6
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//INST(&V::arm_MRRC, "MRRC", "----11000101--------------------"), // v5E
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//INST(&V::arm_STC, "STC2", "1111110----0--------------------"), // v5
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//INST(&V::arm_STC, "STC", "----110----0--------------------"), // v2
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// Data Processing instructions
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ADC_reg, "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ADC_rsr, "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_ADD_imm, "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ADD_reg, "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ADD_rsr, "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_AND_imm, "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_AND_reg, "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_AND_rsr, "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_BIC_imm, "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_BIC_reg, "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_BIC_rsr, "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_CMN_imm, "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_CMN_reg, "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_CMN_rsr, "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm"), // all
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INST(&V::arm_CMP_imm, "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_CMP_reg, "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_CMP_rsr, "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm"), // all
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//INST(&V::arm_EOR_imm, "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_EOR_reg, "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_EOR_rsr, "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_MOV_imm, "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_MOV_reg, "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_MOV_rsr, "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm"), // all
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//INST(&V::arm_MVN_imm, "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_MVN_reg, "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_MVN_rsr, "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm"), // all
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//INST(&V::arm_ORR_imm, "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ORR_reg, "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ORR_rsr, "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_RSB_imm, "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_RSB_reg, "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_RSB_rsr, "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_RSC_imm, "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_RSC_reg, "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_RSC_rsr, "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_SBC_imm, "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_SBC_reg, "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_SBC_rsr, "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_SUB_reg, "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_SUB_rsr, "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_TEQ_imm, "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_TEQ_reg, "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_TEQ_rsr, "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm"), // all
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//INST(&V::arm_TST_imm, "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_TST_reg, "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_TST_rsr, "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm"), // all
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// Data Processing instructions
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ADC_reg, "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ADC_rsr, "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_ADD_imm, "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ADD_reg, "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ADD_rsr, "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_AND_imm, "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_AND_reg, "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_AND_rsr, "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_BIC_imm, "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_BIC_reg, "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_BIC_rsr, "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_CMN_imm, "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_CMN_reg, "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_CMN_rsr, "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm"), // all
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INST(&V::arm_CMP_imm, "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_CMP_reg, "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_CMP_rsr, "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm"), // all
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//INST(&V::arm_EOR_imm, "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_EOR_reg, "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_EOR_rsr, "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_MOV_imm, "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_MOV_reg, "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_MOV_rsr, "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm"), // all
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//INST(&V::arm_MVN_imm, "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_MVN_reg, "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_MVN_rsr, "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm"), // all
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//INST(&V::arm_ORR_imm, "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_ORR_reg, "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_ORR_rsr, "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_RSB_imm, "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_RSB_reg, "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_RSB_rsr, "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_RSC_imm, "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_RSC_reg, "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_RSC_rsr, "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_SBC_imm, "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_SBC_reg, "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_SBC_rsr, "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv"), // all
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//INST(&V::arm_SUB_reg, "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm"), // all
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//INST(&V::arm_SUB_rsr, "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm"), // all
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//INST(&V::arm_TEQ_imm, "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_TEQ_reg, "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_TEQ_rsr, "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm"), // all
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//INST(&V::arm_TST_imm, "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv"), // all
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//INST(&V::arm_TST_reg, "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm"), // all
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//INST(&V::arm_TST_rsr, "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm"), // all
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// Exception Generating instructions
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//INST(&V::arm_BKPT, "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv"), // v5
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INST(&V::arm_SVC, "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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INST(&V::arm_UDF, "UDF", "111001111111------------1111----"), // all
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// Exception Generating instructions
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//INST(&V::arm_BKPT, "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv"), // v5
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INST(&V::arm_SVC, "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv"), // all
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INST(&V::arm_UDF, "UDF", "111001111111------------1111----"), // all
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// Extension instructions
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//INST(&V::arm_SXTB, "SXTB", "cccc011010101111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTB16, "SXTB16", "cccc011010001111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTH, "SXTH", "cccc011010111111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAB, "SXTAB", "cccc01101010nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAB16, "SXTAB16", "cccc01101000nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAH, "SXTAH", "cccc01101011nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTB, "UXTB", "cccc011011101111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTB16, "UXTB16", "cccc011011001111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTH, "UXTH", "cccc011011111111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAB, "UXTAB", "cccc01101110nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAB16, "UXTAB16", "cccc01101100nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm"), // v6
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// Extension instructions
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//INST(&V::arm_SXTB, "SXTB", "cccc011010101111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTB16, "SXTB16", "cccc011010001111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTH, "SXTH", "cccc011010111111ddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAB, "SXTAB", "cccc01101010nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAB16, "SXTAB16", "cccc01101000nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_SXTAH, "SXTAH", "cccc01101011nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTB, "UXTB", "cccc011011101111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTB16, "UXTB16", "cccc011011001111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTH, "UXTH", "cccc011011111111ddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAB, "UXTAB", "cccc01101110nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAB16, "UXTAB16", "cccc01101100nnnnddddrr000111mmmm"), // v6
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//INST(&V::arm_UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm"), // v6
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// Hint instructions
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//INST(&V::arm_PLD, "PLD", "111101---101----1111------------"), // v5E
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//INST(&V::arm_SEV, "SEV", "----0011001000001111000000000100"), // v6K
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//INST(&V::arm_WFE, "WFE", "----0011001000001111000000000010"), // v6K
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//INST(&V::arm_WFI, "WFI", "----0011001000001111000000000011"), // v6K
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//INST(&V::arm_YIELD, "YIELD", "----0011001000001111000000000001"), // v6K
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// Hint instructions
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//INST(&V::arm_PLD, "PLD", "111101---101----1111------------"), // v5E
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//INST(&V::arm_SEV, "SEV", "----0011001000001111000000000100"), // v6K
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//INST(&V::arm_WFE, "WFE", "----0011001000001111000000000010"), // v6K
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//INST(&V::arm_WFI, "WFI", "----0011001000001111000000000011"), // v6K
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//INST(&V::arm_YIELD, "YIELD", "----0011001000001111000000000001"), // v6K
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// Synchronization Primitive instructions
|
||||
//INST(&V::arm_CLREX, "CLREX", "11110101011111111111000000011111"), // v6K
|
||||
//INST(&V::arm_LDREX, "LDREX", "cccc00011001nnnndddd111110011111"), // v6
|
||||
//INST(&V::arm_LDREXB, "LDREXB", "cccc00011101nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_LDREXD, "LDREXD", "cccc00011011nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_LDREXH, "LDREXH", "cccc00011111nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_STREX, "STREX", "cccc00011000nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_STREXB, "STREXB", "cccc00011100nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_STREXD, "STREXD", "cccc00011010nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_STREXH, "STREXH", "cccc00011110nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_SWP, "SWP", "cccc00010000nnnndddd00001001mmmm"), // v2S (v6: Deprecated)
|
||||
//INST(&V::arm_SWPB, "SWPB", "cccc00010100nnnndddd00001001mmmm"), // v2S (v6: Deprecated)
|
||||
// Synchronization Primitive instructions
|
||||
//INST(&V::arm_CLREX, "CLREX", "11110101011111111111000000011111"), // v6K
|
||||
//INST(&V::arm_LDREX, "LDREX", "cccc00011001nnnndddd111110011111"), // v6
|
||||
//INST(&V::arm_LDREXB, "LDREXB", "cccc00011101nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_LDREXD, "LDREXD", "cccc00011011nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_LDREXH, "LDREXH", "cccc00011111nnnndddd111110011111"), // v6K
|
||||
//INST(&V::arm_STREX, "STREX", "cccc00011000nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_STREXB, "STREXB", "cccc00011100nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_STREXD, "STREXD", "cccc00011010nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_STREXH, "STREXH", "cccc00011110nnnndddd11111001mmmm"), // v6K
|
||||
//INST(&V::arm_SWP, "SWP", "cccc00010000nnnndddd00001001mmmm"), // v2S (v6: Deprecated)
|
||||
//INST(&V::arm_SWPB, "SWPB", "cccc00010100nnnndddd00001001mmmm"), // v2S (v6: Deprecated)
|
||||
|
||||
// Load/Store instructions
|
||||
//INST(&V::arm_LDR_imm, "LDR (imm)", "cccc010pu0w1nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_LDR_reg, "LDR (reg)", "cccc011pu0w1nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_LDRBT, "LDRBT (A1)", "----0100-111--------------------"),
|
||||
//INST(&V::arm_LDRBT, "LDRBT (A2)", "----0110-111---------------0----"),
|
||||
//INST(&V::arm_LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnddddvvvv1101vvvv"), // v5E
|
||||
//INST(&V::arm_LDRD_reg, "LDRD (reg)", "cccc000pu0w0nnnndddd00001101mmmm"), // v5E
|
||||
//INST(&V::arm_LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnddddvvvv1011vvvv"),
|
||||
//INST(&V::arm_LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnndddd00001011mmmm"),
|
||||
//INST(&V::arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----"),
|
||||
//INST(&V::arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----"),
|
||||
//INST(&V::arm_LDRSB_imm, "LDRSB (imm)", "cccc000pu1w1nnnnddddvvvv1101vvvv"),
|
||||
//INST(&V::arm_LDRSB_reg, "LDRSB (reg)", "cccc000pu0w1nnnndddd00001101mmmm"),
|
||||
//INST(&V::arm_LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----"),
|
||||
//INST(&V::arm_LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----"),
|
||||
//INST(&V::arm_LDRSH_imm, "LDRSH (imm)", "cccc000pu1w1nnnnddddvvvv1111vvvv"),
|
||||
//INST(&V::arm_LDRSH_reg, "LDRSH (reg)", "cccc000pu0w1nnnndddd00001111mmmm"),
|
||||
//INST(&V::arm_LDRSHT, "LDRSHT (A1)", "----0000-111------------1111----"),
|
||||
//INST(&V::arm_LDRSHT, "LDRSHT (A2)", "----0000-011--------00001111----"),
|
||||
//INST(&V::arm_LDRT, "LDRT (A1)", "----0100-011--------------------"),
|
||||
//INST(&V::arm_LDRT, "LDRT (A2)", "----0110-011---------------0----"),
|
||||
//INST(&V::arm_STR_imm, "STR (imm)", "cccc010pu0w0nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_STR_reg, "STR (reg)", "cccc011pu0w0nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_STRB_imm, "STRB (imm)", "cccc010pu1w0nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_STRBT, "STRBT (A1)", "----0100-110--------------------"),
|
||||
//INST(&V::arm_STRBT, "STRBT (A2)", "----0110-110---------------0----"),
|
||||
//INST(&V::arm_STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnddddvvvv1111vvvv"), // v5E
|
||||
//INST(&V::arm_STRD_reg, "STRD (reg)", "cccc000pu0w0nnnndddd00001111mmmm"), // v5E
|
||||
//INST(&V::arm_STRH_imm, "STRH (imm)", "cccc000pu1w0nnnnddddvvvv1011vvvv"),
|
||||
//INST(&V::arm_STRH_reg, "STRH (reg)", "cccc000pu0w0nnnndddd00001011mmmm"),
|
||||
//INST(&V::arm_STRHT, "STRHT (A1)", "----0000-110------------1011----"),
|
||||
//INST(&V::arm_STRHT, "STRHT (A2)", "----0000-010--------00001011----"),
|
||||
//INST(&V::arm_STRT, "STRT (A1)", "----0100-010--------------------"),
|
||||
//INST(&V::arm_STRT, "STRT (A2)", "----0110-010---------------0----"),
|
||||
// Load/Store instructions
|
||||
//INST(&V::arm_LDR_imm, "LDR (imm)", "cccc010pu0w1nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_LDR_reg, "LDR (reg)", "cccc011pu0w1nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_LDRBT, "LDRBT (A1)", "----0100-111--------------------"),
|
||||
//INST(&V::arm_LDRBT, "LDRBT (A2)", "----0110-111---------------0----"),
|
||||
//INST(&V::arm_LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnddddvvvv1101vvvv"), // v5E
|
||||
//INST(&V::arm_LDRD_reg, "LDRD (reg)", "cccc000pu0w0nnnndddd00001101mmmm"), // v5E
|
||||
//INST(&V::arm_LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnddddvvvv1011vvvv"),
|
||||
//INST(&V::arm_LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnndddd00001011mmmm"),
|
||||
//INST(&V::arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----"),
|
||||
//INST(&V::arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----"),
|
||||
//INST(&V::arm_LDRSB_imm, "LDRSB (imm)", "cccc000pu1w1nnnnddddvvvv1101vvvv"),
|
||||
//INST(&V::arm_LDRSB_reg, "LDRSB (reg)", "cccc000pu0w1nnnndddd00001101mmmm"),
|
||||
//INST(&V::arm_LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----"),
|
||||
//INST(&V::arm_LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----"),
|
||||
//INST(&V::arm_LDRSH_imm, "LDRSH (imm)", "cccc000pu1w1nnnnddddvvvv1111vvvv"),
|
||||
//INST(&V::arm_LDRSH_reg, "LDRSH (reg)", "cccc000pu0w1nnnndddd00001111mmmm"),
|
||||
//INST(&V::arm_LDRSHT, "LDRSHT (A1)", "----0000-111------------1111----"),
|
||||
//INST(&V::arm_LDRSHT, "LDRSHT (A2)", "----0000-011--------00001111----"),
|
||||
//INST(&V::arm_LDRT, "LDRT (A1)", "----0100-011--------------------"),
|
||||
//INST(&V::arm_LDRT, "LDRT (A2)", "----0110-011---------------0----"),
|
||||
//INST(&V::arm_STR_imm, "STR (imm)", "cccc010pu0w0nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_STR_reg, "STR (reg)", "cccc011pu0w0nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_STRB_imm, "STRB (imm)", "cccc010pu1w0nnnnddddvvvvvvvvvvvv"),
|
||||
//INST(&V::arm_STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnddddvvvvvrr0mmmm"),
|
||||
//INST(&V::arm_STRBT, "STRBT (A1)", "----0100-110--------------------"),
|
||||
//INST(&V::arm_STRBT, "STRBT (A2)", "----0110-110---------------0----"),
|
||||
//INST(&V::arm_STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnddddvvvv1111vvvv"), // v5E
|
||||
//INST(&V::arm_STRD_reg, "STRD (reg)", "cccc000pu0w0nnnndddd00001111mmmm"), // v5E
|
||||
//INST(&V::arm_STRH_imm, "STRH (imm)", "cccc000pu1w0nnnnddddvvvv1011vvvv"),
|
||||
//INST(&V::arm_STRH_reg, "STRH (reg)", "cccc000pu0w0nnnndddd00001011mmmm"),
|
||||
//INST(&V::arm_STRHT, "STRHT (A1)", "----0000-110------------1011----"),
|
||||
//INST(&V::arm_STRHT, "STRHT (A2)", "----0000-010--------00001011----"),
|
||||
//INST(&V::arm_STRT, "STRT (A1)", "----0100-010--------------------"),
|
||||
//INST(&V::arm_STRT, "STRT (A2)", "----0110-010---------------0----"),
|
||||
|
||||
// Load/Store Multiple instructions
|
||||
//INST(&V::arm_LDM, "LDM", "cccc100pu0w1nnnnxxxxxxxxxxxxxxxx"), // all
|
||||
//INST(&V::arm_LDM_usr, "LDM (usr reg)", "----100--101--------------------"), // all
|
||||
//INST(&V::arm_LDM_eret, "LDM (exce ret)", "----100--1-1----1---------------"), // all
|
||||
//INST(&V::arm_STM, "STM", "cccc100pu0w0nnnnxxxxxxxxxxxxxxxx"), // all
|
||||
//INST(&V::arm_STM_usr, "STM (usr reg)", "----100--100--------------------"), // all
|
||||
// Load/Store Multiple instructions
|
||||
//INST(&V::arm_LDM, "LDM", "cccc100pu0w1nnnnxxxxxxxxxxxxxxxx"), // all
|
||||
//INST(&V::arm_LDM_usr, "LDM (usr reg)", "----100--101--------------------"), // all
|
||||
//INST(&V::arm_LDM_eret, "LDM (exce ret)", "----100--1-1----1---------------"), // all
|
||||
//INST(&V::arm_STM, "STM", "cccc100pu0w0nnnnxxxxxxxxxxxxxxxx"), // all
|
||||
//INST(&V::arm_STM_usr, "STM (usr reg)", "----100--100--------------------"), // all
|
||||
|
||||
// Miscellaneous instructions
|
||||
//INST(&V::arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm"), // v5
|
||||
//INST(&V::arm_NOP, "NOP", "----001100100000111100000000----"), // v6K
|
||||
//INST(&V::arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm"), // v6
|
||||
// Miscellaneous instructions
|
||||
//INST(&V::arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm"), // v5
|
||||
//INST(&V::arm_NOP, "NOP", "----001100100000111100000000----"), // v6K
|
||||
//INST(&V::arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm"), // v6
|
||||
|
||||
// Unsigned Sum of Absolute Differences instructions
|
||||
//INST(&V::arm_USAD8, "USAD8", "cccc01111000dddd1111mmmm0001nnnn"), // v6
|
||||
//INST(&V::arm_USADA8, "USADA8", "cccc01111000ddddaaaammmm0001nnnn"), // v6
|
||||
// Unsigned Sum of Absolute Differences instructions
|
||||
//INST(&V::arm_USAD8, "USAD8", "cccc01111000dddd1111mmmm0001nnnn"), // v6
|
||||
//INST(&V::arm_USADA8, "USADA8", "cccc01111000ddddaaaammmm0001nnnn"), // v6
|
||||
|
||||
// Packing instructions
|
||||
//INST(&V::arm_PKHBT, "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm"), // v6K
|
||||
//INST(&V::arm_PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm"), // v6K
|
||||
// Packing instructions
|
||||
//INST(&V::arm_PKHBT, "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm"), // v6K
|
||||
//INST(&V::arm_PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm"), // v6K
|
||||
|
||||
// Reversal instructions
|
||||
INST(&V::arm_REV, "REV", "cccc011010111111dddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_REV16, "REV16", "cccc011010111111dddd11111011mmmm"), // v6
|
||||
INST(&V::arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm"), // v6
|
||||
// Reversal instructions
|
||||
INST(&V::arm_REV, "REV", "cccc011010111111dddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_REV16, "REV16", "cccc011010111111dddd11111011mmmm"), // v6
|
||||
INST(&V::arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm"), // v6
|
||||
|
||||
// Saturation instructions
|
||||
//INST(&V::arm_SSAT, "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn"), // v6
|
||||
//INST(&V::arm_SSAT16, "SSAT16", "cccc01101010vvvvdddd11110011nnnn"), // v6
|
||||
//INST(&V::arm_USAT, "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn"), // v6
|
||||
//INST(&V::arm_USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn"), // v6
|
||||
// Saturation instructions
|
||||
//INST(&V::arm_SSAT, "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn"), // v6
|
||||
//INST(&V::arm_SSAT16, "SSAT16", "cccc01101010vvvvdddd11110011nnnn"), // v6
|
||||
//INST(&V::arm_USAT, "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn"), // v6
|
||||
//INST(&V::arm_USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn"), // v6
|
||||
|
||||
// Multiply (Normal) instructions
|
||||
//INST(&V::arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn"), // v2
|
||||
//INST(&V::arm_MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn"), // v2
|
||||
// Multiply (Normal) instructions
|
||||
//INST(&V::arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn"), // v2
|
||||
//INST(&V::arm_MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn"), // v2
|
||||
|
||||
// Multiply (Long) instructions
|
||||
//INST(&V::arm_SMLAL, "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_SMULL, "SMULL", "cccc0000110Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_UMAAL, "UMAAL", "cccc00000100ddddaaaammmm1001nnnn"), // v6
|
||||
//INST(&V::arm_UMLAL, "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_UMULL, "UMULL", "cccc0000100Sddddaaaammmm1001nnnn"), // v3M
|
||||
// Multiply (Long) instructions
|
||||
//INST(&V::arm_SMLAL, "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_SMULL, "SMULL", "cccc0000110Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_UMAAL, "UMAAL", "cccc00000100ddddaaaammmm1001nnnn"), // v6
|
||||
//INST(&V::arm_UMLAL, "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn"), // v3M
|
||||
//INST(&V::arm_UMULL, "UMULL", "cccc0000100Sddddaaaammmm1001nnnn"), // v3M
|
||||
|
||||
// Multiply (Halfword) instructions
|
||||
//INST(&V::arm_SMLALxy, "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn"), // v5xP
|
||||
//INST(&V::arm_SMLAxy, "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn"), // v5xP
|
||||
//INST(&V::arm_SMULxy, "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn"), // v5xP
|
||||
// Multiply (Halfword) instructions
|
||||
//INST(&V::arm_SMLALxy, "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn"), // v5xP
|
||||
//INST(&V::arm_SMLAxy, "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn"), // v5xP
|
||||
//INST(&V::arm_SMULxy, "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn"), // v5xP
|
||||
|
||||
// Multiply (Word by Halfword) instructions
|
||||
//INST(&V::arm_SMLAWy, "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn"), // v5xP
|
||||
//INST(&V::arm_SMULWy, "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn"), // v5xP
|
||||
// Multiply (Word by Halfword) instructions
|
||||
//INST(&V::arm_SMLAWy, "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn"), // v5xP
|
||||
//INST(&V::arm_SMULWy, "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn"), // v5xP
|
||||
|
||||
// Multiply (Most Significant Word) instructions
|
||||
//INST(&V::arm_SMMUL, "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn"), // v6
|
||||
//INST(&V::arm_SMMLA, "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn"), // v6
|
||||
//INST(&V::arm_SMMLS, "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn"), // v6
|
||||
// Multiply (Most Significant Word) instructions
|
||||
//INST(&V::arm_SMMUL, "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn"), // v6
|
||||
//INST(&V::arm_SMMLA, "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn"), // v6
|
||||
//INST(&V::arm_SMMLS, "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn"), // v6
|
||||
|
||||
// Multiply (Dual) instructions
|
||||
//INST(&V::arm_SMLAD, "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLALD, "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLSD, "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLSLD, "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn"), // v6
|
||||
//INST(&V::arm_SMUAD, "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMUSD, "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn"), // v6
|
||||
// Multiply (Dual) instructions
|
||||
//INST(&V::arm_SMLAD, "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLALD, "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLSD, "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn"), // v6
|
||||
//INST(&V::arm_SMLSLD, "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn"), // v6
|
||||
//INST(&V::arm_SMUAD, "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn"), // v6
|
||||
//INST(&V::arm_SMUSD, "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn"), // v6
|
||||
|
||||
// Parallel Add/Subtract (Modulo) instructions
|
||||
//INST(&V::arm_SADD8, "SADD8", "cccc01100001nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_SADD16, "SADD16", "cccc01100001nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_SASX, "SASX", "cccc01100001nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_SSAX, "SSAX", "cccc01100001nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_SSUB8, "SSUB8", "cccc01100001nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_SSUB16, "SSUB16", "cccc01100001nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UADD8, "UADD8", "cccc01100101nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UADD16, "UADD16", "cccc01100101nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UASX, "UASX", "cccc01100101nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_USAX, "USAX", "cccc01100101nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_USUB8, "USUB8", "cccc01100101nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_USUB16, "USUB16", "cccc01100101nnnndddd11110111mmmm"), // v6
|
||||
// Parallel Add/Subtract (Modulo) instructions
|
||||
//INST(&V::arm_SADD8, "SADD8", "cccc01100001nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_SADD16, "SADD16", "cccc01100001nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_SASX, "SASX", "cccc01100001nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_SSAX, "SSAX", "cccc01100001nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_SSUB8, "SSUB8", "cccc01100001nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_SSUB16, "SSUB16", "cccc01100001nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UADD8, "UADD8", "cccc01100101nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UADD16, "UADD16", "cccc01100101nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UASX, "UASX", "cccc01100101nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_USAX, "USAX", "cccc01100101nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_USUB8, "USUB8", "cccc01100101nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_USUB16, "USUB16", "cccc01100101nnnndddd11110111mmmm"), // v6
|
||||
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
//INST(&V::arm_QADD8, "QADD8", "cccc01100010nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_QADD16, "QADD16", "cccc01100010nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_QASX, "QASX", "cccc01100010nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_QSAX, "QSAX", "cccc01100010nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_QSUB8, "QSUB8", "cccc01100010nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_QSUB16, "QSUB16", "cccc01100010nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UQADD8, "UQADD8", "cccc01100110nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UQADD16, "UQADD16", "cccc01100110nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UQASX, "UQASX", "cccc01100110nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_UQSAX, "UQSAX", "cccc01100110nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_UQSUB8, "UQSUB8", "cccc01100110nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_UQSUB16, "UQSUB16", "cccc01100110nnnndddd11110111mmmm"), // v6
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
//INST(&V::arm_QADD8, "QADD8", "cccc01100010nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_QADD16, "QADD16", "cccc01100010nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_QASX, "QASX", "cccc01100010nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_QSAX, "QSAX", "cccc01100010nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_QSUB8, "QSUB8", "cccc01100010nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_QSUB16, "QSUB16", "cccc01100010nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UQADD8, "UQADD8", "cccc01100110nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UQADD16, "UQADD16", "cccc01100110nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UQASX, "UQASX", "cccc01100110nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_UQSAX, "UQSAX", "cccc01100110nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_UQSUB8, "UQSUB8", "cccc01100110nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_UQSUB16, "UQSUB16", "cccc01100110nnnndddd11110111mmmm"), // v6
|
||||
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
//INST(&V::arm_SHADD8, "SHADD8", "cccc01100011nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_SHADD16, "SHADD16", "cccc01100011nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_SHASX, "SHASX", "cccc01100011nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_SHSAX, "SHSAX", "cccc01100011nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_SHSUB8, "SHSUB8", "cccc01100011nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_SHSUB16, "SHSUB16", "cccc01100011nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UHADD8, "UHADD8", "cccc01100111nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UHADD16, "UHADD16", "cccc01100111nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UHASX, "UHASX", "cccc01100111nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_UHSAX, "UHSAX", "cccc01100111nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_UHSUB8, "UHSUB8", "cccc01100111nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_UHSUB16, "UHSUB16", "cccc01100111nnnndddd11110111mmmm"), // v6
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
//INST(&V::arm_SHADD8, "SHADD8", "cccc01100011nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_SHADD16, "SHADD16", "cccc01100011nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_SHASX, "SHASX", "cccc01100011nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_SHSAX, "SHSAX", "cccc01100011nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_SHSUB8, "SHSUB8", "cccc01100011nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_SHSUB16, "SHSUB16", "cccc01100011nnnndddd11110111mmmm"), // v6
|
||||
//INST(&V::arm_UHADD8, "UHADD8", "cccc01100111nnnndddd11111001mmmm"), // v6
|
||||
//INST(&V::arm_UHADD16, "UHADD16", "cccc01100111nnnndddd11110001mmmm"), // v6
|
||||
//INST(&V::arm_UHASX, "UHASX", "cccc01100111nnnndddd11110011mmmm"), // v6
|
||||
//INST(&V::arm_UHSAX, "UHSAX", "cccc01100111nnnndddd11110101mmmm"), // v6
|
||||
//INST(&V::arm_UHSUB8, "UHSUB8", "cccc01100111nnnndddd11111111mmmm"), // v6
|
||||
//INST(&V::arm_UHSUB16, "UHSUB16", "cccc01100111nnnndddd11110111mmmm"), // v6
|
||||
|
||||
// Saturated Add/Subtract instructions
|
||||
//INST(&V::arm_QADD, "QADD", "cccc00010000nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QSUB, "QSUB", "cccc00010010nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QDADD, "QDADD", "cccc00010100nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QDSUB, "QDSUB", "cccc00010110nnnndddd00000101mmmm"), // v5xP
|
||||
// Saturated Add/Subtract instructions
|
||||
//INST(&V::arm_QADD, "QADD", "cccc00010000nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QSUB, "QSUB", "cccc00010010nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QDADD, "QDADD", "cccc00010100nnnndddd00000101mmmm"), // v5xP
|
||||
//INST(&V::arm_QDSUB, "QDSUB", "cccc00010110nnnndddd00000101mmmm"), // v5xP
|
||||
|
||||
// Status Register Access instructions
|
||||
//INST(&V::arm_CPS, "CPS", "111100010000---00000000---0-----"), // v6
|
||||
//INST(&V::arm_SETEND, "SETEND", "1111000100000001000000e000000000"), // v6
|
||||
//INST(&V::arm_MRS, "MRS", "----00010-00--------00--00000000"), // v3
|
||||
//INST(&V::arm_MSR, "MSR", "----00-10-10----1111------------"), // v3
|
||||
//INST(&V::arm_RFE, "RFE", "----0001101-0000---------110----"), // v6
|
||||
//INST(&V::arm_SRS, "SRS", "0000011--0-00000000000000001----"), // v6
|
||||
// Status Register Access instructions
|
||||
//INST(&V::arm_CPS, "CPS", "111100010000---00000000---0-----"), // v6
|
||||
//INST(&V::arm_SETEND, "SETEND", "1111000100000001000000e000000000"), // v6
|
||||
//INST(&V::arm_MRS, "MRS", "----00010-00--------00--00000000"), // v3
|
||||
//INST(&V::arm_MSR, "MSR", "----00-10-10----1111------------"), // v3
|
||||
//INST(&V::arm_RFE, "RFE", "----0001101-0000---------110----"), // v6
|
||||
//INST(&V::arm_SRS, "SRS", "0000011--0-00000000000000001----"), // v6
|
||||
|
||||
#undef INST
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
template<typename Visitor>
|
||||
boost::optional<const ArmMatcher<Visitor>&> DecodeArm(u32 instruction) {
|
||||
const auto& table = g_arm_instruction_table<Visitor>;
|
||||
const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); };
|
||||
const auto matches_instruction = [instruction](const auto& matcher) { return matcher.Matches(instruction); };
|
||||
|
||||
auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
|
||||
return iter != table.end() ? boost::make_optional<const ArmMatcher<Visitor>&>(*iter) : boost::none;
|
||||
return iter != table.end() ? boost::make_optional<const ArmMatcher<V>&>(*iter) : boost::none;
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
|
|
@ -98,6 +98,10 @@ private:
|
|||
template<typename FnT, FnT fn>
|
||||
struct VisitorCaller;
|
||||
|
||||
#ifdef _MSC_VER
|
||||
#pragma warning(push)
|
||||
#pragma warning(disable:4800)
|
||||
#endif
|
||||
template<typename Visitor, typename ...Args, typename CallRetT, CallRetT (Visitor::*fn)(Args...)>
|
||||
struct VisitorCaller<CallRetT(Visitor::*)(Args...), fn> {
|
||||
template<size_t ...iota>
|
||||
|
|
@ -110,6 +114,9 @@ private:
|
|||
};
|
||||
}
|
||||
};
|
||||
#ifdef _MSC_VER
|
||||
#pragma warning(pop)
|
||||
#endif
|
||||
|
||||
public:
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
#include <array>
|
||||
#include <functional>
|
||||
#include <tuple>
|
||||
#include <vector>
|
||||
|
||||
#include <boost/optional.hpp>
|
||||
|
||||
|
|
@ -55,111 +55,109 @@ private:
|
|||
std::function<CallRetT(Visitor&, u16)> fn;
|
||||
};
|
||||
|
||||
template <typename V>
|
||||
const std::array<Thumb16Matcher<V>, 44> g_thumb16_instruction_table = {
|
||||
template<typename V>
|
||||
boost::optional<const Thumb16Matcher<V>&> DecodeThumb16(u16 instruction) {
|
||||
const static std::vector<Thumb16Matcher<V>> table = {
|
||||
|
||||
#define INST(fn, name, bitstring) detail::detail<Thumb16Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
|
||||
|
||||
// Shift (immediate), add, subtract, move and compare instructions
|
||||
INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"),
|
||||
INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"),
|
||||
INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"),
|
||||
INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"),
|
||||
INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"),
|
||||
INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"),
|
||||
INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"),
|
||||
INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"),
|
||||
INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"),
|
||||
INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"),
|
||||
INST(&V::thumb16_SUB_imm_t2, "SUB (imm, T2)", "00111dddvvvvvvvv"),
|
||||
// Shift (immediate), add, subtract, move and compare instructions
|
||||
INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"),
|
||||
INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"),
|
||||
INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"),
|
||||
INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"),
|
||||
INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"),
|
||||
INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"),
|
||||
INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"),
|
||||
INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"),
|
||||
INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"),
|
||||
INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"),
|
||||
INST(&V::thumb16_SUB_imm_t2, "SUB (imm, T2)", "00111dddvvvvvvvv"),
|
||||
|
||||
// Data-processing instructions
|
||||
INST(&V::thumb16_AND_reg, "AND (reg)", "0100000000mmmddd"),
|
||||
INST(&V::thumb16_EOR_reg, "EOR (reg)", "0100000001mmmddd"),
|
||||
INST(&V::thumb16_LSL_reg, "LSL (reg)", "0100000010mmmddd"),
|
||||
INST(&V::thumb16_LSR_reg, "LSR (reg)", "0100000011mmmddd"),
|
||||
INST(&V::thumb16_ASR_reg, "ASR (reg)", "0100000100mmmddd"),
|
||||
INST(&V::thumb16_ADC_reg, "ADC (reg)", "0100000101mmmddd"),
|
||||
INST(&V::thumb16_SBC_reg, "SBC (reg)", "0100000110mmmddd"),
|
||||
INST(&V::thumb16_ROR_reg, "ROR (reg)", "0100000111sssddd"),
|
||||
INST(&V::thumb16_TST_reg, "TST (reg)", "0100001000mmmnnn"),
|
||||
INST(&V::thumb16_RSB_imm, "RSB (imm)", "0100001001nnnddd"),
|
||||
INST(&V::thumb16_CMP_reg_t1, "CMP (reg, T1)", "0100001010mmmnnn"),
|
||||
INST(&V::thumb16_CMN_reg, "CMN (reg)", "0100001011mmmnnn"),
|
||||
INST(&V::thumb16_ORR_reg, "ORR (reg)", "0100001100mmmddd"),
|
||||
//INST(&V::thumb16_MULS_rr, "MULS (rr)", "0100001101mmmddd"),
|
||||
INST(&V::thumb16_BIC_reg, "BIC (reg)", "0100001110mmmddd"),
|
||||
INST(&V::thumb16_MVN_reg, "MVN (reg)", "0100001111mmmddd"),
|
||||
// Data-processing instructions
|
||||
INST(&V::thumb16_AND_reg, "AND (reg)", "0100000000mmmddd"),
|
||||
INST(&V::thumb16_EOR_reg, "EOR (reg)", "0100000001mmmddd"),
|
||||
INST(&V::thumb16_LSL_reg, "LSL (reg)", "0100000010mmmddd"),
|
||||
INST(&V::thumb16_LSR_reg, "LSR (reg)", "0100000011mmmddd"),
|
||||
INST(&V::thumb16_ASR_reg, "ASR (reg)", "0100000100mmmddd"),
|
||||
INST(&V::thumb16_ADC_reg, "ADC (reg)", "0100000101mmmddd"),
|
||||
INST(&V::thumb16_SBC_reg, "SBC (reg)", "0100000110mmmddd"),
|
||||
INST(&V::thumb16_ROR_reg, "ROR (reg)", "0100000111sssddd"),
|
||||
INST(&V::thumb16_TST_reg, "TST (reg)", "0100001000mmmnnn"),
|
||||
INST(&V::thumb16_RSB_imm, "RSB (imm)", "0100001001nnnddd"),
|
||||
INST(&V::thumb16_CMP_reg_t1, "CMP (reg, T1)", "0100001010mmmnnn"),
|
||||
INST(&V::thumb16_CMN_reg, "CMN (reg)", "0100001011mmmnnn"),
|
||||
INST(&V::thumb16_ORR_reg, "ORR (reg)", "0100001100mmmddd"),
|
||||
//INST(&V::thumb16_MULS_rr, "MULS (rr)", "0100001101mmmddd"),
|
||||
INST(&V::thumb16_BIC_reg, "BIC (reg)", "0100001110mmmddd"),
|
||||
INST(&V::thumb16_MVN_reg, "MVN (reg)", "0100001111mmmddd"),
|
||||
|
||||
// Special data instructions
|
||||
INST(&V::thumb16_ADD_reg_t2, "ADD (reg, T2)", "01000100Dmmmmddd"), // v4T, Low regs: v6T2
|
||||
INST(&V::thumb16_CMP_reg_t2, "CMP (reg, T2)", "01000101Nmmmmnnn"), // v4T
|
||||
INST(&V::thumb16_MOV_reg, "MOV (reg)", "01000110Dmmmmddd"), // v4T, Low regs: v6
|
||||
// Special data instructions
|
||||
INST(&V::thumb16_ADD_reg_t2, "ADD (reg, T2)", "01000100Dmmmmddd"), // v4T, Low regs: v6T2
|
||||
INST(&V::thumb16_CMP_reg_t2, "CMP (reg, T2)", "01000101Nmmmmnnn"), // v4T
|
||||
INST(&V::thumb16_MOV_reg, "MOV (reg)", "01000110Dmmmmddd"), // v4T, Low regs: v6
|
||||
|
||||
// Store/Load single data item instructions
|
||||
INST(&V::thumb16_LDR_literal, "LDR (literal)", "01001tttvvvvvvvv"),
|
||||
INST(&V::thumb16_STR_reg, "STR (reg)", "0101000mmmnnnttt"),
|
||||
INST(&V::thumb16_STRH_reg, "STRH (reg)", "0101001mmmnnnttt"),
|
||||
INST(&V::thumb16_STRB_reg, "STRB (reg)", "0101010mmmnnnttt"),
|
||||
//INST(&V::thumb16_LDRSB_rrr, "LDRSB (rrr)", "0101011mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDR_rrr, "LDR (rrr)", "0101100mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRH_rrr, "LDRH (rrr)", "0101101mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRB_rrr, "LDRB (rrr)", "0101110mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRSH_rrr, "LDRSH (rrr)", "0101111mmmnnnddd"),
|
||||
INST(&V::thumb16_LDR_imm_t1, "LDR (imm, T1)", "01101vvvvvnnnttt"),
|
||||
//INST(&V::thumb16_STRH_rri, "STRH (rri)", "10000vvvvvnnnddd"),
|
||||
//INST(&V::thumb16_LDRH_rri, "LDRH (rri)", "10001vvvvvnnnddd"),
|
||||
//INST(&V::thumb16_STR_sp, "STR (SP)", "10010dddvvvvvvvv"),
|
||||
//INST(&V::thumb16_LDR_sp, "LDR (SP)", "10011dddvvvvvvvv"),
|
||||
// Store/Load single data item instructions
|
||||
INST(&V::thumb16_LDR_literal, "LDR (literal)", "01001tttvvvvvvvv"),
|
||||
INST(&V::thumb16_STR_reg, "STR (reg)", "0101000mmmnnnttt"),
|
||||
INST(&V::thumb16_STRH_reg, "STRH (reg)", "0101001mmmnnnttt"),
|
||||
INST(&V::thumb16_STRB_reg, "STRB (reg)", "0101010mmmnnnttt"),
|
||||
//INST(&V::thumb16_LDRSB_rrr, "LDRSB (rrr)", "0101011mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDR_rrr, "LDR (rrr)", "0101100mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRH_rrr, "LDRH (rrr)", "0101101mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRB_rrr, "LDRB (rrr)", "0101110mmmnnnddd"),
|
||||
//INST(&V::thumb16_LDRSH_rrr, "LDRSH (rrr)", "0101111mmmnnnddd"),
|
||||
INST(&V::thumb16_LDR_imm_t1, "LDR (imm, T1)", "01101vvvvvnnnttt"),
|
||||
//INST(&V::thumb16_STRH_rri, "STRH (rri)", "10000vvvvvnnnddd"),
|
||||
//INST(&V::thumb16_LDRH_rri, "LDRH (rri)", "10001vvvvvnnnddd"),
|
||||
//INST(&V::thumb16_STR_sp, "STR (SP)", "10010dddvvvvvvvv"),
|
||||
//INST(&V::thumb16_LDR_sp, "LDR (SP)", "10011dddvvvvvvvv"),
|
||||
|
||||
// Generate relative address instruction
|
||||
INST(&V::thumb16_ADR, "ADR", "10100dddvvvvvvvv"),
|
||||
//INST(&V::thumb16_ADD_sp, "ADD (relative to SP)", "10101dddvvvvvvvv"),
|
||||
// Generate relative address instruction
|
||||
INST(&V::thumb16_ADR, "ADR", "10100dddvvvvvvvv"),
|
||||
//INST(&V::thumb16_ADD_sp, "ADD (relative to SP)", "10101dddvvvvvvvv"),
|
||||
|
||||
// Miscellaneous 16-bit instructions
|
||||
//INST(&V::thumb16_ADD_spsp, "ADD (imm to SP)", "101100000vvvvvvv"), // v4T
|
||||
//INST(&V::thumb16_SUB_spsp, "SUB (imm from SP)", "101100001vvvvvvv"), // v4T
|
||||
INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6
|
||||
INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6
|
||||
INST(&V::thumb16_UXTH, "UXTH", "1011001010mmmddd"), // v6
|
||||
INST(&V::thumb16_UXTB, "UXTB", "1011001011mmmddd"), // v6
|
||||
//INST(&V::thumb16_PUSH, "PUSH", "1011010rxxxxxxxx"), // v4T
|
||||
//INST(&V::thumb16_POP, "POP", "1011110rxxxxxxxx"), // v4T
|
||||
//INST(&V::thumb16_SETEND, "SETEND", "101101100101x000"), // v6
|
||||
//INST(&V::thumb16_CPS, "CPS", "10110110011m0aif"), // v6
|
||||
INST(&V::thumb16_REV, "REV", "1011101000mmmddd"), // v6
|
||||
INST(&V::thumb16_REV16, "REV16", "1011101001mmmddd"), // v6
|
||||
INST(&V::thumb16_REVSH, "REVSH", "1011101011mmmddd"), // v6
|
||||
//INST(&V::thumb16_BKPT, "BKPT", "10111110xxxxxxxx"), // v5
|
||||
// Miscellaneous 16-bit instructions
|
||||
//INST(&V::thumb16_ADD_spsp, "ADD (imm to SP)", "101100000vvvvvvv"), // v4T
|
||||
//INST(&V::thumb16_SUB_spsp, "SUB (imm from SP)", "101100001vvvvvvv"), // v4T
|
||||
INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6
|
||||
INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6
|
||||
INST(&V::thumb16_UXTH, "UXTH", "1011001010mmmddd"), // v6
|
||||
INST(&V::thumb16_UXTB, "UXTB", "1011001011mmmddd"), // v6
|
||||
//INST(&V::thumb16_PUSH, "PUSH", "1011010rxxxxxxxx"), // v4T
|
||||
//INST(&V::thumb16_POP, "POP", "1011110rxxxxxxxx"), // v4T
|
||||
//INST(&V::thumb16_SETEND, "SETEND", "101101100101x000"), // v6
|
||||
//INST(&V::thumb16_CPS, "CPS", "10110110011m0aif"), // v6
|
||||
INST(&V::thumb16_REV, "REV", "1011101000mmmddd"), // v6
|
||||
INST(&V::thumb16_REV16, "REV16", "1011101001mmmddd"), // v6
|
||||
INST(&V::thumb16_REVSH, "REVSH", "1011101011mmmddd"), // v6
|
||||
//INST(&V::thumb16_BKPT, "BKPT", "10111110xxxxxxxx"), // v5
|
||||
|
||||
// Store/Load multiple registers
|
||||
//INST(&V::thumb16_STMIA, "STMIA", "11000nnnxxxxxxxx"),
|
||||
//INST(&V::thumb16_LDMIA, "LDMIA", "11001nnnxxxxxxxx"),
|
||||
// Store/Load multiple registers
|
||||
//INST(&V::thumb16_STMIA, "STMIA", "11000nnnxxxxxxxx"),
|
||||
//INST(&V::thumb16_LDMIA, "LDMIA", "11001nnnxxxxxxxx"),
|
||||
|
||||
// Branch instructions
|
||||
//INST(&V::thumb16_BX, "BX (reg)", "010001110mmmm000"), // v4T
|
||||
//INST(&V::thumb16_BLX, "BLX (reg)", "010001111mmmm000"), // v5T
|
||||
INST(&V::thumb16_UDF, "UDF", "11011110--------"),
|
||||
INST(&V::thumb16_SVC, "SVC", "11011111xxxxxxxx"),
|
||||
//INST(&V::thumb16_B_cond, "B (cond)", "1101ccccxxxxxxxx"),
|
||||
//INST(&V::thumb16_B_imm, "B (imm)", "11100xxxxxxxxxxx"),
|
||||
//INST(&V::thumb16_BLX_suffix, "BLX (imm, suffix)", "11101xxxxxxxxxx0"),
|
||||
//INST(&V::thumb16_BLX_prefix, "BL/BLX (imm, prefix)", "11110xxxxxxxxxxx"),
|
||||
//INST(&V::thumb16_BL_suffix, "BL (imm, suffix)", "11111xxxxxxxxxxx"),
|
||||
// Branch instructions
|
||||
//INST(&V::thumb16_BX, "BX (reg)", "010001110mmmm000"), // v4T
|
||||
//INST(&V::thumb16_BLX, "BLX (reg)", "010001111mmmm000"), // v5T
|
||||
INST(&V::thumb16_UDF, "UDF", "11011110--------"),
|
||||
INST(&V::thumb16_SVC, "SVC", "11011111xxxxxxxx"),
|
||||
//INST(&V::thumb16_B_cond, "B (cond)", "1101ccccxxxxxxxx"),
|
||||
//INST(&V::thumb16_B_imm, "B (imm)", "11100xxxxxxxxxxx"),
|
||||
//INST(&V::thumb16_BLX_suffix, "BLX (imm, suffix)", "11101xxxxxxxxxx0"),
|
||||
//INST(&V::thumb16_BLX_prefix, "BL/BLX (imm, prefix)", "11110xxxxxxxxxxx"),
|
||||
//INST(&V::thumb16_BL_suffix, "BL (imm, suffix)", "11111xxxxxxxxxxx"),
|
||||
|
||||
#undef INST
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
template<typename Visitor>
|
||||
boost::optional<const Thumb16Matcher<Visitor>&> DecodeThumb16(u16 instruction) {
|
||||
const auto& table = g_thumb16_instruction_table<Visitor>;
|
||||
auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); };
|
||||
const auto matches_instruction = [instruction](const auto& matcher){ return matcher.Matches(instruction); };
|
||||
|
||||
assert(std::count_if(table.begin(), table.end(), matches_instruction) <= 1);
|
||||
|
||||
auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
|
||||
return iter != table.end() ? boost::make_optional<const Thumb16Matcher<Visitor>&>(*iter) : boost::none;
|
||||
return iter != table.end() ? boost::make_optional<const Thumb16Matcher<V>&>(*iter) : boost::none;
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ public:
|
|||
protected:
|
||||
friend class Inst;
|
||||
|
||||
Value(Opcode op_) : op(op_) {}
|
||||
explicit Value(Opcode op_) : op(op_) {}
|
||||
|
||||
void AddUse(ValuePtr owner);
|
||||
void RemoveUse(ValuePtr owner);
|
||||
|
|
@ -98,7 +98,7 @@ private:
|
|||
};
|
||||
std::list<Use> uses;
|
||||
|
||||
intptr_t tag;
|
||||
intptr_t tag = 0;
|
||||
};
|
||||
|
||||
/// Representation of a u1 immediate.
|
||||
|
|
|
|||
|
|
@ -80,13 +80,13 @@ struct ArmTranslatorVisitor final {
|
|||
return true;
|
||||
}
|
||||
|
||||
u32 rotr(u32 x, int shift) {
|
||||
static u32 rotr(u32 x, int shift) {
|
||||
shift &= 31;
|
||||
if (!shift) return x;
|
||||
return (x >> shift) | (x << (32 - shift));
|
||||
}
|
||||
|
||||
u32 ArmExpandImm(int rotate, Imm8 imm8) {
|
||||
static u32 ArmExpandImm(int rotate, Imm8 imm8) {
|
||||
return rotr(static_cast<u32>(imm8), rotate*2);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -527,7 +527,7 @@ enum class ThumbInstSize {
|
|||
Thumb16, Thumb32
|
||||
};
|
||||
|
||||
static std::tuple<u32, ThumbInstSize> ReadThumbInstruction(u32 arm_pc, MemoryRead32FuncType memory_read_32) {
|
||||
std::tuple<u32, ThumbInstSize> ReadThumbInstruction(u32 arm_pc, MemoryRead32FuncType memory_read_32) {
|
||||
u32 first_part = (*memory_read_32)(arm_pc & 0xFFFFFFFC);
|
||||
if ((arm_pc & 0x2) != 0)
|
||||
first_part >>= 16;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue