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Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic

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This commit is contained in:
MerryMage 2016-07-18 10:33:52 +01:00
commit bf99ddd065
4 changed files with 73 additions and 8 deletions
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6
src/frontend/decoder/arm.h
View file

@ -59,7 +59,7 @@ private:
};
template <typename V>
static const std::array<ArmMatcher<V>, 4> g_arm_instruction_table = {
static const std::array<ArmMatcher<V>, 6> g_arm_instruction_table = {
#define INST(fn, name, bitstring) detail::detail<ArmMatcher, u32, 32>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -235,9 +235,9 @@ static const std::array<ArmMatcher<V>, 4> g_arm_instruction_table = {
//INST(&V::arm_PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm"), // v6K
// Reversal instructions
//INST(&V::arm_REV, "REV", "cccc011010111111dddd11110011mmmm"), // v6
INST(&V::arm_REV, "REV", "cccc011010111111dddd11110011mmmm"), // v6
//INST(&V::arm_REV16, "REV16", "cccc011010111111dddd11111011mmmm"), // v6
//INST(&V::arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm"), // v6
INST(&V::arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm"), // v6
// Saturation instructions
//INST(&V::arm_SSAT, "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn"), // v6

12
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -405,9 +405,15 @@ public:
std::string arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { return "ice"; }
// Reversal instructions
std::string arm_REV(Cond cond, Reg d, Reg m) { return "ice"; }
std::string arm_REV16(Cond cond, Reg d, Reg m) { return "ice"; }
std::string arm_REVSH(Cond cond, Reg d, Reg m) { return "ice"; }
std::string arm_REV(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("rev%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
}
std::string arm_REV16(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("rev16%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
}
std::string arm_REVSH(Cond cond, Reg d, Reg m) {
return Common::StringFromFormat("revsh%s %s, %s", CondStr(cond), RegStr(d), RegStr(m));
}
// Saturation instructions
std::string arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) { return "ice"; }

26
src/frontend/translate/translate_arm.cpp
View file

@ -280,6 +280,32 @@ struct ArmTranslatorVisitor final {
bool arm_UDF() {
return InterpretThisInstruction();
}
bool arm_REV(Cond cond, Reg d, Reg m) {
// REV<c> <Rd>, <Rm>
ASSERT(d != Reg::PC && m != Reg::PC);
if (ConditionPassed(cond)) {
auto result = ir.ByteReverseWord(ir.GetRegister(m));
ir.SetRegister(d, result);
}
return true;
}
bool arm_REV16(Cond cond, Reg d, Reg m) {
return InterpretThisInstruction();
}
bool arm_REVSH(Cond cond, Reg d, Reg m) {
// REVSH<c> <Rd>, <Rm>
ASSERT(d != Reg::PC && m != Reg::PC);
if (ConditionPassed(cond)) {
auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
}
return true;
}
};
} // local namespace