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A32: Implement ASIMD VMAX, VMIN (floating-point)

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This commit is contained in:
MerryMage 2020-06-20 01:18:17 +01:00
parent 8d067d5d60
commit bb4f3aa407
7 changed files with 100 additions and 52 deletions
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4
src/frontend/A32/decoder/asimd.inc
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@ -43,8 +43,8 @@ INST(asimd_VMUL, "VMUL", "1111001P0Dzznnnndddd100
//INST(asimd_VCGE_reg, "VCGE (register)", "111100110-0C--------1110---0----") // ASIMD
//INST(asimd_VCGT_reg, "VCGT (register)", "111100110-1C--------1110---0----") // ASIMD
//INST(asimd_VACGE, "VACGE", "111100110-CC--------1110---1----") // ASIMD
//INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100-CC--------1111---0----") // ASIMD
//INST(asimd_VPMAX_float, "VMIN (floating-point)", "111100110-CC--------1111---0----") // ASIMD
INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD
INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD
//INST(asimd_VRECPS, "VRECPS", "111100100-0C--------1111---1----") // ASIMD
//INST(asimd_VRSQRTS, "VRSQRTS", "111100100-1C--------1111---1----") // ASIMD

42
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -333,4 +333,46 @@ bool ArmTranslatorVisitor::asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size
return true;
}
bool ArmTranslatorVisitor::asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b1) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_n = ir.GetVector(n);
const auto reg_m = ir.GetVector(m);
const auto result = ir.FPVectorMax(32, reg_m, reg_n, false);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b1) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_n = ir.GetVector(n);
const auto reg_m = ir.GetVector(m);
const auto result = ir.FPVectorMin(32, reg_m, reg_n, false);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32

2
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -462,6 +462,8 @@ struct ArmTranslatorVisitor final {
bool asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Two registers and a shift amount
bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);