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IR: Implement VectorMultiply

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This commit is contained in:
MerryMage 2018-02-11 10:18:29 +00:00
parent 90a053a5e4
commit b6de612e01
4 changed files with 92 additions and 0 deletions
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15
src/frontend/ir/ir_emitter.cpp
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@ -913,6 +913,21 @@ U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_am
return {};
}
U128 IREmitter::VectorMultiply(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorMultiply8, a, b);
case 16:
return Inst<U128>(Opcode::VectorMultiply16, a, b);
case 32:
return Inst<U128>(Opcode::VectorMultiply32, a, b);
case 64:
return Inst<U128>(Opcode::VectorMultiply64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorNarrow(size_t original_esize, const U128& a) {
switch (original_esize) {
case 16:

1
src/frontend/ir/ir_emitter.h
View file

@ -217,6 +217,7 @@ public:
U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b);
U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
U128 VectorMultiply(size_t esize, const U128& a, const U128& b);
U128 VectorNarrow(size_t original_esize, const U128& a);
U128 VectorNot(const U128& a);
U128 VectorOr(const U128& a, const U128& b);

4
src/frontend/ir/opcodes.inc
View file

@ -232,6 +232,10 @@ OPCODE(VectorLogicalShiftRight8, T::U128, T::U128, T::U8
OPCODE(VectorLogicalShiftRight16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight64, T::U128, T::U128, T::U8 )
OPCODE(VectorMultiply8, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply16, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply32, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply64, T::U128, T::U128, T::U128 )
OPCODE(VectorNarrow16, T::U128, T::U128 )
OPCODE(VectorNarrow32, T::U128, T::U128 )
OPCODE(VectorNarrow64, T::U128, T::U128 )