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Implement VCVT
This commit is contained in:
MerryMage
parent
445aad0639
commit
b5a86889cd
8 changed files with 447 additions and 3 deletions
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@ -1211,6 +1211,13 @@ static void DefaultNaN64(BlockOfCode* code, X64Reg xmm_value) {
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code->SetJumpTarget(fixup);
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}
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static void ZeroIfNaN64(BlockOfCode* code, X64Reg xmm_value) {
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code->UCOMISD(xmm_value, R(xmm_value));
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auto fixup = code->J_CC(CC_NP);
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code->MOVAPS(xmm_value, code->MFloatPositiveZero64());
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code->SetJumpTarget(fixup);
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}
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static void FPThreeOp32(BlockOfCode* code, RegAlloc& reg_alloc, IR::Block& block, IR::Inst* inst, void (XEmitter::*fn)(X64Reg, const OpArg&)) {
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IR::Value a = inst->GetArg(0);
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IR::Value b = inst->GetArg(1);
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@ -1389,6 +1396,283 @@ void EmitX64::EmitFPSub64(IR::Block& block, IR::Inst* inst) {
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FPThreeOp64(code, reg_alloc, block, inst, &XEmitter::SUBSD);
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}
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void EmitX64::EmitFPSingleToDouble(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero32(code, result, gpr_scratch);
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}
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code->CVTSS2SD(result, R(result));
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if (block.location.FPSCR_FTZ()) {
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FlushToZero64(code, result, gpr_scratch);
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}
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if (block.location.FPSCR_DN()) {
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DefaultNaN64(code, result);
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}
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}
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void EmitX64::EmitFPDoubleToSingle(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero64(code, result, gpr_scratch);
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}
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code->CVTSD2SS(result, R(result));
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if (block.location.FPSCR_FTZ()) {
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FlushToZero32(code, result, gpr_scratch);
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}
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if (block.location.FPSCR_DN()) {
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DefaultNaN32(code, result);
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}
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}
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void EmitX64::EmitFPSingleToS32(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_towards_zero = inst->GetArg(1).GetU1();
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X64Reg from = reg_alloc.UseScratchRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
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// Conversion to double is lossless, and allows for clamping.
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero32(code, from, gpr_scratch);
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}
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code->CVTSS2SD(from, R(from));
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// First time is to set flags
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if (round_towards_zero) {
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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} else {
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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}
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// Clamp to output range
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ZeroIfNaN64(code, from);
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinS32());
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// Second time is for real
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if (round_towards_zero) {
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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} else {
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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}
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code->MOVD_xmm(to, R(gpr_scratch));
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}
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void EmitX64::EmitFPSingleToU32(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_towards_zero = inst->GetArg(1).GetU1();
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X64Reg from = reg_alloc.UseScratchRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
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// Conversion to double is lossless, and allows for accurate clamping.
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//
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// Since SSE2 doesn't provide an unsigned conversion, we shift the range as appropriate.
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//
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// FIXME: Inexact exception not correctly signalled with the below code
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if (block.location.FPSCR_RMode() != Arm::FPRoundingMode::RoundTowardsZero && !round_towards_zero) {
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero32(code, from, gpr_scratch);
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}
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code->CVTSS2SD(from, R(from));
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ZeroIfNaN64(code, from);
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// Bring into SSE range
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code->ADDSD(from, code->MFloatMinS32());
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// First time is to set flags
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Clamp to output range
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinS32());
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// Actually convert
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Bring back into original range
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code->ADD(32, R(gpr_scratch), Imm32(2147483648u));
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code->MOVQ_xmm(to, R(gpr_scratch));
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} else {
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X64Reg xmm_mask = reg_alloc.ScratchRegister(any_xmm);
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X64Reg gpr_mask = reg_alloc.ScratchRegister(any_gpr);
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero32(code, from, gpr_scratch);
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}
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code->CVTSS2SD(from, R(from));
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ZeroIfNaN64(code, from);
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// Generate masks if out-of-signed-range
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code->MOVAPS(xmm_mask, code->MFloatMaxS32());
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code->CMPLTSD(xmm_mask, R(from));
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code->MOVQ_xmm(R(gpr_mask), xmm_mask);
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code->PAND(xmm_mask, code->MFloatMinS32());
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code->AND(32, R(gpr_mask), Imm32(2147483648u));
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// Bring into range if necessary
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code->ADDSD(from, R(xmm_mask));
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// First time is to set flags
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Clamp to output range
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinU32());
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// Actually convert
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Bring back into original range if necessary
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code->ADD(32, R(gpr_scratch), R(gpr_mask));
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code->MOVQ_xmm(to, R(gpr_scratch));
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}
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}
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void EmitX64::EmitFPDoubleToS32(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_towards_zero = inst->GetArg(1).GetU1();
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X64Reg from = reg_alloc.UseScratchRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero64(code, from, gpr_scratch);
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}
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// First time is to set flags
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if (round_towards_zero) {
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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} else {
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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}
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// Clamp to output range
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ZeroIfNaN64(code, from);
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinS32());
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// Second time is for real
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if (round_towards_zero) {
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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} else {
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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}
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code->MOVD_xmm(to, R(gpr_scratch));
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}
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void EmitX64::EmitFPDoubleToU32(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_towards_zero = inst->GetArg(1).GetU1();
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X64Reg from = reg_alloc.UseScratchRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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X64Reg xmm_scratch = reg_alloc.ScratchRegister(any_xmm);
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// ARM saturates on conversion; this differs from x64 which returns a sentinel value.
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// TODO: Use VCVTPD2UDQ when AVX512VL is available.
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// FIXME: Inexact exception not correctly signalled with the below code
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if (block.location.FPSCR_RMode() != Arm::FPRoundingMode::RoundTowardsZero && !round_towards_zero) {
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero64(code, from, gpr_scratch);
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}
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ZeroIfNaN64(code, from);
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// Bring into SSE range
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code->ADDSD(from, code->MFloatMinS32());
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// First time is to set flags
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Clamp to output range
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinS32());
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// Actually convert
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code->CVTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Bring back into original range
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code->ADD(32, R(gpr_scratch), Imm32(2147483648u));
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code->MOVQ_xmm(to, R(gpr_scratch));
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} else {
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X64Reg xmm_mask = reg_alloc.ScratchRegister(any_xmm);
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X64Reg gpr_mask = reg_alloc.ScratchRegister(any_gpr);
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if (block.location.FPSCR_FTZ()) {
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DenormalsAreZero64(code, from, gpr_scratch);
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}
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ZeroIfNaN64(code, from);
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// Generate masks if out-of-signed-range
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code->MOVAPS(xmm_mask, code->MFloatMaxS32());
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code->CMPLTSD(xmm_mask, R(from));
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code->MOVQ_xmm(R(gpr_mask), xmm_mask);
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code->PAND(xmm_mask, code->MFloatMinS32());
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code->AND(32, R(gpr_mask), Imm32(2147483648u));
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// Bring into range if necessary
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code->ADDSD(from, R(xmm_mask));
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// First time is to set flags
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Clamp to output range
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code->MINSD(from, code->MFloatMaxS32());
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code->MAXSD(from, code->MFloatMinU32());
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// Actually convert
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code->CVTTSD2SI(gpr_scratch, R(from)); // 32 bit gpr
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// Bring back into original range if necessary
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code->ADD(32, R(gpr_scratch), R(gpr_mask));
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code->MOVQ_xmm(to, R(gpr_scratch));
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}
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}
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void EmitX64::EmitFPS32ToSingle(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_to_nearest = inst->GetArg(1).GetU1();
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ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
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X64Reg from = reg_alloc.UseRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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code->MOVD_xmm(R(gpr_scratch), from);
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code->CVTSI2SS(32, to, R(gpr_scratch));
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}
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void EmitX64::EmitFPU32ToSingle(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_to_nearest = inst->GetArg(1).GetU1();
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ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
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X64Reg from = reg_alloc.UseRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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code->MOVD_xmm(R(gpr_scratch), from);
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code->CVTSI2SS(64, to, R(gpr_scratch));
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}
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void EmitX64::EmitFPS32ToDouble(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_to_nearest = inst->GetArg(1).GetU1();
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ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
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X64Reg from = reg_alloc.UseRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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code->MOVD_xmm(R(gpr_scratch), from);
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code->CVTSI2SD(32, to, R(gpr_scratch));
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}
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void EmitX64::EmitFPU32ToDouble(IR::Block& block, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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bool round_to_nearest = inst->GetArg(1).GetU1();
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ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
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X64Reg from = reg_alloc.UseRegister(a, any_xmm);
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X64Reg to = reg_alloc.DefRegister(inst, any_xmm);
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X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
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code->MOVD_xmm(R(gpr_scratch), from);
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code->CVTSI2SD(64, to, R(gpr_scratch));
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}
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void EmitX64::EmitClearExclusive(IR::Block&, IR::Inst*) {
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code->MOV(8, MDisp(R15, offsetof(JitState, exclusive_state)), Imm8(0));
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}
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