Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-01 12:14:50 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A64: Implement FRSQRTS (vector), single/double variant

Browse source
This commit is contained in:
MerryMage 2018-07-23 22:58:52 +01:00
parent 45dc5f74f3
commit b2e4c16ef8
7 changed files with 123 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -739,7 +739,7 @@ INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001
INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
//INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")
INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")

66
src/frontend/A64/translate/impl/impl.h
View file

@ -404,40 +404,22 @@ struct TranslatorVisitor final {
// Data Processing - FP and SIMD - Scalar three
bool FMULX_vec_1(Vec Vm, Vec Vn, Vec Vd);
bool FMULX_vec_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMULX_vec_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMULX_vec_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_1(Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_1(Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_1(Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_1(Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGE_1(Vec Vm, Vec Vn, Vec Vd);
bool FACGE_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGE_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FABD_1(Vec Vm, Vec Vn, Vec Vd);
bool FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FABD_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_1(Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGT_1(Vec Vm, Vec Vn, Vec Vd);
bool FACGT_2(bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGT_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - Two register misc FP16
bool FCVTNS_1(Vec Vn, Vec Vd);
@ -697,36 +679,30 @@ struct TranslatorVisitor final {
bool INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD Three same
bool FMULX_vec_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FACGE_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FABD_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FACGT_3(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMLA_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMLA_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FADD_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAX_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAX_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINNM_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMINNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMLS_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMLS_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FSUB_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMIN_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMIN_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FADDP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FADDP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMUL_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMUL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAXP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAXP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FDIV_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FDIV_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMINNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMINP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD Two-register misc
bool FRINTN_1(bool Q, Vec Vn, Vec Vd);
@ -854,6 +830,30 @@ struct TranslatorVisitor final {
bool BSL(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool BIT(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool BIF(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMLA_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAX_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINNM_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMLS_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMIN_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAXNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FADDP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMUL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMAXP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FDIV_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINNMP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMINP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FMULX_vec_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRECPS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
bool FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD modified immediate
bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);

14
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -592,6 +592,20 @@ bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FRSQRTS_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t esize = sz ? 64 : 32;
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.FPVectorRSqrtStepFused(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;

11
src/frontend/ir/ir_emitter.cpp
View file

@ -1690,6 +1690,17 @@ U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
return {};
}
U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorRSqrtStepFused32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:

1
src/frontend/ir/ir_emitter.h
View file

@ -300,6 +300,7 @@ public:
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorS32ToSingle(const U128& a);
U128 FPVectorS64ToDouble(const U128& a);

2
src/frontend/ir/opcodes.inc
View file

@ -437,6 +437,8 @@ OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U
OPCODE(FPVectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate64, T::U128, T::U128 )
OPCODE(FPVectorRSqrtStepFused32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRSqrtStepFused64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )
OPCODE(FPVectorS64ToDouble, T::U128, T::U128 )
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )