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IR: Implement VectorLogicalShiftRight
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4 changed files with 73 additions and 0 deletions
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@ -883,6 +883,21 @@ U128 IREmitter::VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amo
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return {};
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}
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U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) {
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switch (esize) {
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case 8:
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return Inst<U128>(Opcode::VectorLogicalShiftRight8, a, Imm8(shift_amount));
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case 16:
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return Inst<U128>(Opcode::VectorLogicalShiftRight16, a, Imm8(shift_amount));
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case 32:
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return Inst<U128>(Opcode::VectorLogicalShiftRight32, a, Imm8(shift_amount));
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case 64:
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return Inst<U128>(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount));
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}
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UNREACHABLE();
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return {};
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}
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U128 IREmitter::VectorNot(const U128& a) {
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return Inst<U128>(Opcode::VectorNot, a);
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}
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@ -215,6 +215,7 @@ public:
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U128 VectorEqual(size_t esize, const U128& a, const U128& b);
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U128 VectorInterleaveLower(size_t esize, const U128& a, const U128& b);
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U128 VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amount);
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U128 VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount);
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U128 VectorNot(const U128& a);
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U128 VectorOr(const U128& a, const U128& b);
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U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
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@ -224,6 +224,10 @@ OPCODE(VectorLogicalShiftLeft8, T::U128, T::U128, T::U8
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OPCODE(VectorLogicalShiftLeft16, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftLeft32, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftLeft64, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftRight8, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftRight16, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftRight32, T::U128, T::U128, T::U8 )
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OPCODE(VectorLogicalShiftRight64, T::U128, T::U128, T::U8 )
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OPCODE(VectorNot, T::U128, T::U128 )
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OPCODE(VectorOr, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAddLower8, T::U128, T::U128, T::U128 )
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