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A32: Implement ASIMD VMLA, VMLS (floating-point)
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60f6e729ac
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3 changed files with 18 additions and 1 deletions
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@ -381,6 +381,20 @@ bool ArmTranslatorVisitor::asimd_VABD_float(bool D, bool sz, size_t Vn, size_t V
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});
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}
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bool ArmTranslatorVisitor::asimd_VMLA_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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const auto product = ir.FPVectorMul(32, reg_n, reg_m, false);
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return ir.FPVectorAdd(32, reg_d, product, false);
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});
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}
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bool ArmTranslatorVisitor::asimd_VMLS_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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const auto product = ir.FPVectorMul(32, reg_n, reg_m, false);
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return ir.FPVectorAdd(32, reg_d, ir.FPVectorNeg(32, product), false);
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});
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}
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bool ArmTranslatorVisitor::asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) {
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return ir.FPVectorMul(32, reg_n, reg_m, false);
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