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A64: Implement system register CNTPCT_EL0

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This commit is contained in:
MerryMage 2018-02-20 16:54:10 +00:00
parent 1e15283d00
commit 9e4e4e9c1d
8 changed files with 29 additions and 2 deletions
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4
src/frontend/A64/ir_emitter.cpp
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@ -53,6 +53,10 @@ void IREmitter::DataMemoryBarrier() {
Inst(Opcode::A64DataMemoryBarrier);
}
IR::U64 IREmitter::GetCNTPCT() {
return Inst<IR::U64>(Opcode::A64GetCNTPCT);
}
IR::U32 IREmitter::GetCTR() {
return Inst<IR::U32>(Opcode::A64GetCTR);
}

1
src/frontend/A64/ir_emitter.h
View file

@ -44,6 +44,7 @@ public:
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
void DataSynchronizationBarrier();
void DataMemoryBarrier();
IR::U64 GetCNTPCT(); // TODO: Ensure sub-basic-block cycle counts are updated before this.
IR::U32 GetCTR();
IR::U32 GetDCZID();
IR::U64 GetTPIDRRO();

3
src/frontend/A64/translate/impl/system.cpp
View file

@ -63,6 +63,9 @@ bool TranslatorVisitor::MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3
case 0b11'011'0000'0000'001: // CTR_EL0
X(32, Rt, ir.GetCTR());
return true;
case 0b11'011'1110'0000'001: // CNTPCT_EL0
X(64, Rt, ir.GetCNTPCT());
return true;
}
return InterpretThisInstruction();
}

1
src/frontend/ir/opcodes.inc
View file

@ -61,6 +61,7 @@ A64OPC(ExceptionRaised, T::Void, T::U64, T::U64
A64OPC(DataCacheOperationRaised, T::Void, T::U64, T::U64 )
A64OPC(DataSynchronizationBarrier, T::Void, )
A64OPC(DataMemoryBarrier, T::Void, )
A64OPC(GetCNTPCT, T::U64, )
A64OPC(GetCTR, T::U32, )
A64OPC(GetDCZID, T::U32, )
A64OPC(GetTPIDRRO, T::U64, )