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A32: Change UserCallbacks to be similar to A64's interface
This commit is contained in:
MerryMage
parent
b9ce660113
commit
98ec9c5f90
21 changed files with 472 additions and 622 deletions
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@ -26,133 +26,17 @@
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#include "frontend/ir/basic_block.h"
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#include "ir_opt/passes.h"
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#include "rand_int.h"
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#include "testenv.h"
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#include "A32/skyeye_interpreter/dyncom/arm_dyncom_interpreter.h"
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#include "A32/skyeye_interpreter/skyeye_common/armstate.h"
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struct WriteRecord {
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size_t size;
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u32 address;
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u64 data;
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};
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static bool operator==(const WriteRecord& a, const WriteRecord& b) {
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return std::tie(a.size, a.address, a.data) == std::tie(b.size, b.address, b.data);
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static Dynarmic::A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
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Dynarmic::A32::UserConfig user_config;
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user_config.callbacks = testenv;
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return user_config;
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}
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static u64 jit_num_ticks = 0;
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static std::array<u16, 3000> code_mem{};
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static std::vector<WriteRecord> write_records;
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static u64 GetTicksRemaining();
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static void AddTicks(u64 ticks);
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static bool IsReadOnlyMemory(u32 vaddr);
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static u8 MemoryRead8(u32 vaddr);
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static u16 MemoryRead16(u32 vaddr);
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static u32 MemoryRead32(u32 vaddr);
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static u64 MemoryRead64(u32 vaddr);
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static void MemoryWrite8(u32 vaddr, u8 value);
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static void MemoryWrite16(u32 vaddr, u16 value);
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static void MemoryWrite32(u32 vaddr, u32 value);
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static void MemoryWrite64(u32 vaddr, u64 value);
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static void InterpreterFallback(u32 pc, Dynarmic::A32::Jit* jit, void*);
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static Dynarmic::A32::UserCallbacks GetUserCallbacks();
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static u64 GetTicksRemaining() {
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return jit_num_ticks;
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}
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static void AddTicks(u64 ticks) {
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if (ticks > jit_num_ticks) {
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jit_num_ticks = 0;
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return;
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}
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jit_num_ticks -= ticks;
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}
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static bool IsReadOnlyMemory(u32 vaddr) {
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return vaddr < code_mem.size();
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}
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static u8 MemoryRead8(u32 vaddr) {
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return static_cast<u8>(vaddr);
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}
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static u16 MemoryRead16(u32 vaddr) {
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return static_cast<u16>(vaddr);
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}
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static u32 MemoryRead32(u32 vaddr) {
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if (vaddr < code_mem.size() * sizeof(u16)) {
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size_t index = vaddr / sizeof(u16);
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if (index + 1 >= code_mem.size())
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return code_mem[index];
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return code_mem[index] | (code_mem[index+1] << 16);
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}
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return vaddr;
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}
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static u64 MemoryRead64(u32 vaddr) {
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return vaddr;
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}
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static u32 MemoryReadCode(u32 vaddr) {
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if (vaddr < code_mem.size() * sizeof(u16)) {
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size_t index = vaddr / sizeof(u16);
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if (index + 1 >= code_mem.size())
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return code_mem[index];
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return code_mem[index] | (code_mem[index + 1] << 16);
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}
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return 0xE7FEE7FE; // b +#0, b +#0
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}
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static void MemoryWrite8(u32 vaddr, u8 value){
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write_records.push_back({8, vaddr, value});
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}
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static void MemoryWrite16(u32 vaddr, u16 value){
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write_records.push_back({16, vaddr, value});
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}
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static void MemoryWrite32(u32 vaddr, u32 value){
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write_records.push_back({32, vaddr, value});
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}
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static void MemoryWrite64(u32 vaddr, u64 value){
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write_records.push_back({64, vaddr, value});
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}
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static void InterpreterFallback(u32 pc, Dynarmic::A32::Jit* jit, void*) {
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ARMul_State interp_state{USER32MODE};
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interp_state.user_callbacks = GetUserCallbacks();
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interp_state.NumInstrsToExecute = 1;
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interp_state.Reg = jit->Regs();
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interp_state.Cpsr = jit->Cpsr();
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interp_state.Reg[15] = pc;
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InterpreterClearCache();
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InterpreterMainLoop(&interp_state);
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bool T = Dynarmic::Common::Bit<5>(interp_state.Cpsr);
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interp_state.Reg[15] &= T ? 0xFFFFFFFE : 0xFFFFFFFC;
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jit->Regs() = interp_state.Reg;
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jit->SetCpsr(interp_state.Cpsr);
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}
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static void Fail() {
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FAIL();
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}
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static Dynarmic::A32::UserCallbacks GetUserCallbacks() {
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Dynarmic::A32::UserCallbacks user_callbacks{};
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user_callbacks.InterpreterFallback = &InterpreterFallback;
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user_callbacks.CallSVC = (void (*)(u32)) &Fail;
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user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
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user_callbacks.memory.Read8 = &MemoryRead8;
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user_callbacks.memory.Read16 = &MemoryRead16;
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user_callbacks.memory.Read32 = &MemoryRead32;
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user_callbacks.memory.Read64 = &MemoryRead64;
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user_callbacks.memory.ReadCode = &MemoryReadCode;
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user_callbacks.memory.Write8 = &MemoryWrite8;
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user_callbacks.memory.Write16 = &MemoryWrite16;
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user_callbacks.memory.Write32 = &MemoryWrite32;
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user_callbacks.memory.Write64 = &MemoryWrite64;
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user_callbacks.GetTicksRemaining = &GetTicksRemaining;
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user_callbacks.AddTicks = &AddTicks;
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return user_callbacks;
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}
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using WriteRecords = std::map<u32, u8>;
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struct ThumbInstGen final {
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public:
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@ -193,7 +77,7 @@ private:
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std::function<bool(u16)> is_valid;
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};
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static bool DoesBehaviorMatch(const ARMul_State& interp, const Dynarmic::A32::Jit& jit, const std::vector<WriteRecord>& interp_write_records, const std::vector<WriteRecord>& jit_write_records) {
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static bool DoesBehaviorMatch(const ARMul_State& interp, const Dynarmic::A32::Jit& jit, WriteRecords& interp_write_records, WriteRecords& jit_write_records) {
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const auto interp_regs = interp.Reg;
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const auto jit_regs = jit.Regs();
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@ -202,7 +86,7 @@ static bool DoesBehaviorMatch(const ARMul_State& interp, const Dynarmic::A32::Ji
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&& interp_write_records == jit_write_records;
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}
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static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::Jit& jit, const std::array<u32, 16>& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) {
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static void RunInstance(size_t run_number, ThumbTestEnv& test_env, ARMul_State& interp, Dynarmic::A32::Jit& jit, const std::array<u32, 16>& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) {
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interp.instruction_cache.clear();
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InterpreterClearCache();
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jit.ClearCache();
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@ -215,20 +99,20 @@ static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::J
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jit.Regs() = initial_regs;
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// Run interpreter
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write_records.clear();
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test_env.modified_memory.clear();
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interp.NumInstrsToExecute = static_cast<unsigned>(instructions_to_execute_count);
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InterpreterMainLoop(&interp);
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auto interp_write_records = write_records;
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auto interp_write_records = test_env.modified_memory;
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{
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bool T = Dynarmic::Common::Bit<5>(interp.Cpsr);
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interp.Reg[15] &= T ? 0xFFFFFFFE : 0xFFFFFFFC;
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}
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// Run jit
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write_records.clear();
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jit_num_ticks = instructions_to_execute_count;
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test_env.modified_memory.clear();
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test_env.ticks_left = instructions_to_execute_count;
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jit.Run();
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auto jit_write_records = write_records;
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auto jit_write_records = test_env.modified_memory;
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// Compare
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if (!DoesBehaviorMatch(interp, jit, interp_write_records, jit_write_records)) {
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@ -236,7 +120,7 @@ static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::J
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printf("\nInstruction Listing: \n");
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for (size_t i = 0; i < instruction_count; i++) {
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printf("%04x %s\n", code_mem[i], Dynarmic::A32::DisassembleThumb16(code_mem[i]).c_str());
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printf("%04x %s\n", test_env.code_mem[i], Dynarmic::A32::DisassembleThumb16(test_env.code_mem[i]).c_str());
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}
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printf("\nInitial Register Listing: \n");
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@ -253,12 +137,12 @@ static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::J
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printf("\nInterp Write Records:\n");
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for (auto& record : interp_write_records) {
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printf("%zu [%x] = %" PRIu64 "\n", record.size, record.address, record.data);
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printf("[%08x] = %02x\n", record.first, record.second);
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}
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printf("\nJIT Write Records:\n");
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for (auto& record : jit_write_records) {
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printf("%zu [%x] = %" PRIu64 "\n", record.size, record.address, record.data);
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printf("[%08x] = %02x\n", record.first, record.second);
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}
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Dynarmic::A32::PSR cpsr;
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@ -267,10 +151,10 @@ static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::J
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size_t num_insts = 0;
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while (num_insts < instructions_to_execute_count) {
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Dynarmic::A32::LocationDescriptor descriptor = {u32(num_insts * 4), cpsr, Dynarmic::A32::FPSCR{}};
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Dynarmic::IR::Block ir_block = Dynarmic::A32::Translate(descriptor, &MemoryReadCode);
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Dynarmic::IR::Block ir_block = Dynarmic::A32::Translate(descriptor, [&test_env](u32 vaddr) { return test_env.MemoryReadCode(vaddr); });
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Dynarmic::Optimization::A32GetSetElimination(ir_block);
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Dynarmic::Optimization::DeadCodeElimination(ir_block);
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Dynarmic::Optimization::A32ConstantMemoryReads(ir_block, GetUserCallbacks().memory);
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Dynarmic::Optimization::A32ConstantMemoryReads(ir_block, &test_env);
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Dynarmic::Optimization::ConstantPropagation(ir_block);
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Dynarmic::Optimization::DeadCodeElimination(ir_block);
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Dynarmic::Optimization::VerificationPass(ir_block);
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@ -287,22 +171,24 @@ static void RunInstance(size_t run_number, ARMul_State& interp, Dynarmic::A32::J
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}
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void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_execute_count, const size_t run_count, const std::function<u16()> instruction_generator) {
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ThumbTestEnv test_env;
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// Prepare memory
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code_mem.fill(0xE7FE); // b +#0
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test_env.code_mem.fill(0xE7FE); // b +#0
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// Prepare test subjects
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ARMul_State interp{USER32MODE};
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interp.user_callbacks = GetUserCallbacks();
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Dynarmic::A32::Jit jit{GetUserCallbacks()};
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interp.user_callbacks = &test_env;
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Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
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for (size_t run_number = 0; run_number < run_count; run_number++) {
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std::array<u32, 16> initial_regs;
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std::generate_n(initial_regs.begin(), 15, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
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initial_regs[15] = 0;
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std::generate_n(code_mem.begin(), instruction_count, instruction_generator);
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std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator);
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RunInstance(run_number, interp, jit, initial_regs, instruction_count, instructions_to_execute_count);
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RunInstance(run_number, test_env, interp, jit, initial_regs, instruction_count, instructions_to_execute_count);
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}
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}
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@ -388,13 +274,15 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb]") {
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}
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TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb]") {
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ThumbTestEnv test_env;
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// Prepare memory
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code_mem.fill(0xE7FE); // b +#0
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test_env.code_mem.fill(0xE7FE); // b +#0
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// Prepare test subjects
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ARMul_State interp{USER32MODE};
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interp.user_callbacks = GetUserCallbacks();
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Dynarmic::A32::Jit jit{GetUserCallbacks()};
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interp.user_callbacks = &test_env;
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Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
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std::array<u32, 16> initial_regs {
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0xe90ecd70,
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@ -415,11 +303,11 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb]") {
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0x00000000,
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};
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code_mem[0] = 0x40B8; // lsls r0, r7, #0
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code_mem[1] = 0x01CA; // lsls r2, r1, #7
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code_mem[2] = 0x83A1; // strh r1, [r4, #28]
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code_mem[3] = 0x708A; // strb r2, [r1, #2]
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code_mem[4] = 0xBCC4; // pop {r2, r6, r7}
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test_env.code_mem[0] = 0x40B8; // lsls r0, r7, #0
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test_env.code_mem[1] = 0x01CA; // lsls r2, r1, #7
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test_env.code_mem[2] = 0x83A1; // strh r1, [r4, #28]
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test_env.code_mem[3] = 0x708A; // strb r2, [r1, #2]
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test_env.code_mem[4] = 0xBCC4; // pop {r2, r6, r7}
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RunInstance(1, interp, jit, initial_regs, 5, 5);
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RunInstance(1, test_env, interp, jit, initial_regs, 5, 5);
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}
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