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A32: Implement ASIMD VHADD

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This commit is contained in:
MerryMage 2020-05-28 21:46:44 +01:00
parent f8062345bb
commit 946eb03a3b
3 changed files with 24 additions and 1 deletions
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22
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@ -36,6 +36,28 @@ bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, b
}
} // Anonymous namespace
bool ArmTranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b11) {
return UndefinedInstruction();
}
const size_t esize = 8 << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const IR::U128 reg_n = ir.GetVector(n);
const IR::U128 reg_m = ir.GetVector(m);
const IR::U128 result = U ? ir.VectorHalvingAddUnsigned(esize, reg_n, reg_m) : ir.VectorHalvingAddSigned(esize, reg_n, reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
return ir.VectorAnd(reg_n, reg_m);