Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-04 13:44:31 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A32: Implement ASIMD VMLA/VMLS (integer)

Browse source
This commit is contained in:
Lioncash 2020-06-20 14:41:56 -04:00 • committed by merry
parent 715db8381f
commit 945b757b6c
3 changed files with 28 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

25
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -333,6 +333,31 @@ bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, b
return true;
}
bool ArmTranslatorVisitor::asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_n = ir.GetVector(n);
const auto reg_m = ir.GetVector(m);
const auto reg_d = ir.GetVector(d);
const auto multiply = ir.VectorMultiply(esize, reg_m, reg_n);
const auto result = op ? ir.VectorSub(esize, reg_d, multiply)
: ir.VectorAdd(esize, reg_d, multiply);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (sz == 0b11 || (P && sz != 0b00)) {
return UndefinedInstruction();