A32: Implement ASIMD VRECPS

This commit is contained in:
MerryMage 2020-06-20 14:39:05 +01:00
parent 9eef4f7471
commit 8f506c80c3
7 changed files with 23 additions and 13 deletions

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@ -46,7 +46,7 @@ INST(asimd_VMUL_float, "VMUL (floating-point)", "111100110D0znnnndddd110
//INST(asimd_VACGE, "VACGE", "111100110-CC--------1110---1----") // ASIMD
INST(asimd_VMAX_float, "VMAX (floating-point)", "111100100D0znnnndddd1111NQM0mmmm") // ASIMD
INST(asimd_VMIN_float, "VMIN (floating-point)", "111100100D1znnnndddd1111NQM0mmmm") // ASIMD
//INST(asimd_VRECPS, "VRECPS", "111100100-0C--------1111---1----") // ASIMD
INST(asimd_VRECPS, "VRECPS", "111100100D0znnnndddd1111NQM1mmmm") // ASIMD
//INST(asimd_VRSQRTS, "VRSQRTS", "111100100-1C--------1111---1----") // ASIMD
// Two registers and a scalar

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@ -413,4 +413,10 @@ bool ArmTranslatorVisitor::asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t V
});
}
bool ArmTranslatorVisitor::asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) {
return ir.FPVectorRecipStepFused(32, reg_n, reg_m, false);
});
}
} // namespace Dynarmic::A32

View file

@ -471,6 +471,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VRECPS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Two registers and a shift amount
bool asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);