Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-04 13:44:31 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Standardize indentation of switch statments

Browse source
This commit is contained in:
MerryMage 2016-08-22 23:40:30 +01:00
parent 2471be317e
commit 8d1b9f32ca
12 changed files with 370 additions and 369 deletions
Download patch file Download diff file Expand all files Collapse all files

81
src/ir_opt/dead_code_elimination_pass.cpp
View file

@ -15,46 +15,47 @@ namespace Optimization {
void DeadCodeElimination(IR::Block& block) {
const auto is_side_effect_free = [](IR::Opcode op) -> bool {
switch (op) {
case IR::Opcode::Breakpoint:
case IR::Opcode::SetRegister:
case IR::Opcode::SetExtendedRegister32:
case IR::Opcode::SetExtendedRegister64:
case IR::Opcode::SetNFlag:
case IR::Opcode::SetZFlag:
case IR::Opcode::SetCFlag:
case IR::Opcode::SetVFlag:
case IR::Opcode::OrQFlag:
case IR::Opcode::BXWritePC:
case IR::Opcode::CallSupervisor:
case IR::Opcode::PushRSB:
case IR::Opcode::FPAbs32:
case IR::Opcode::FPAbs64:
case IR::Opcode::FPAdd32:
case IR::Opcode::FPAdd64:
case IR::Opcode::FPDiv32:
case IR::Opcode::FPDiv64:
case IR::Opcode::FPMul32:
case IR::Opcode::FPMul64:
case IR::Opcode::FPNeg32:
case IR::Opcode::FPNeg64:
case IR::Opcode::FPSqrt32:
case IR::Opcode::FPSqrt64:
case IR::Opcode::FPSub32:
case IR::Opcode::FPSub64:
case IR::Opcode::ClearExclusive:
case IR::Opcode::SetExclusive:
case IR::Opcode::WriteMemory8:
case IR::Opcode::WriteMemory16:
case IR::Opcode::WriteMemory32:
case IR::Opcode::WriteMemory64:
case IR::Opcode::ExclusiveWriteMemory8:
case IR::Opcode::ExclusiveWriteMemory16:
case IR::Opcode::ExclusiveWriteMemory32:
case IR::Opcode::ExclusiveWriteMemory64:
return false;
default:
ASSERT(IR::GetTypeOf(op) != IR::Type::Void);
return true;
case IR::Opcode::Breakpoint:
case IR::Opcode::SetRegister:
case IR::Opcode::SetExtendedRegister32:
case IR::Opcode::SetExtendedRegister64:
case IR::Opcode::SetCpsr:
case IR::Opcode::SetNFlag:
case IR::Opcode::SetZFlag:
case IR::Opcode::SetCFlag:
case IR::Opcode::SetVFlag:
case IR::Opcode::OrQFlag:
case IR::Opcode::BXWritePC:
case IR::Opcode::CallSupervisor:
case IR::Opcode::PushRSB:
case IR::Opcode::FPAbs32:
case IR::Opcode::FPAbs64:
case IR::Opcode::FPAdd32:
case IR::Opcode::FPAdd64:
case IR::Opcode::FPDiv32:
case IR::Opcode::FPDiv64:
case IR::Opcode::FPMul32:
case IR::Opcode::FPMul64:
case IR::Opcode::FPNeg32:
case IR::Opcode::FPNeg64:
case IR::Opcode::FPSqrt32:
case IR::Opcode::FPSqrt64:
case IR::Opcode::FPSub32:
case IR::Opcode::FPSub64:
case IR::Opcode::ClearExclusive:
case IR::Opcode::SetExclusive:
case IR::Opcode::WriteMemory8:
case IR::Opcode::WriteMemory16:
case IR::Opcode::WriteMemory32:
case IR::Opcode::WriteMemory64:
case IR::Opcode::ExclusiveWriteMemory8:
case IR::Opcode::ExclusiveWriteMemory16:
case IR::Opcode::ExclusiveWriteMemory32:
case IR::Opcode::ExclusiveWriteMemory64:
return false;
default:
ASSERT(IR::GetTypeOf(op) != IR::Type::Void);
return true;
}
};

112
src/ir_opt/get_set_elimination_pass.cpp
View file

@ -49,63 +49,63 @@ void GetSetElimination(IR::Block& block) {
for (auto inst = block.begin(); inst != block.end(); ++inst) {
switch (inst->GetOpcode()) {
case IR::Opcode::SetRegister: {
Arm::Reg reg = inst->GetArg(0).GetRegRef();
if (reg == Arm::Reg::PC)
break;
size_t reg_index = static_cast<size_t>(reg);
do_set(reg_info[reg_index], inst->GetArg(1), inst);
break;
}
case IR::Opcode::GetRegister: {
Arm::Reg reg = inst->GetArg(0).GetRegRef();
ASSERT(reg != Arm::Reg::PC);
size_t reg_index = static_cast<size_t>(reg);
do_get(reg_info[reg_index], inst);
break;
}
case IR::Opcode::SetNFlag: {
do_set(n_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetNFlag: {
do_get(n_info, inst);
break;
}
case IR::Opcode::SetZFlag: {
do_set(z_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetZFlag: {
do_get(z_info, inst);
break;
}
case IR::Opcode::SetCFlag: {
do_set(c_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetCFlag: {
do_get(c_info, inst);
break;
}
case IR::Opcode::SetVFlag: {
do_set(v_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetVFlag: {
do_get(v_info, inst);
break;
}
case IR::Opcode::SetCpsr:
case IR::Opcode::GetCpsr: {
n_info = {};
z_info = {};
c_info = {};
v_info = {};
break;
}
default:
case IR::Opcode::SetRegister: {
Arm::Reg reg = inst->GetArg(0).GetRegRef();
if (reg == Arm::Reg::PC)
break;
size_t reg_index = static_cast<size_t>(reg);
do_set(reg_info[reg_index], inst->GetArg(1), inst);
break;
}
case IR::Opcode::GetRegister: {
Arm::Reg reg = inst->GetArg(0).GetRegRef();
ASSERT(reg != Arm::Reg::PC);
size_t reg_index = static_cast<size_t>(reg);
do_get(reg_info[reg_index], inst);
break;
}
case IR::Opcode::SetNFlag: {
do_set(n_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetNFlag: {
do_get(n_info, inst);
break;
}
case IR::Opcode::SetZFlag: {
do_set(z_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetZFlag: {
do_get(z_info, inst);
break;
}
case IR::Opcode::SetCFlag: {
do_set(c_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetCFlag: {
do_get(c_info, inst);
break;
}
case IR::Opcode::SetVFlag: {
do_set(v_info, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetVFlag: {
do_get(v_info, inst);
break;
}
case IR::Opcode::SetCpsr:
case IR::Opcode::GetCpsr: {
n_info = {};
z_info = {};
c_info = {};
v_info = {};
break;
}
default:
break;
}
}
}