Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-05 22:18:16 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

IR: Split off A32 specific opcodes

Browse source
This commit is contained in:
MerryMage 2018-01-01 16:19:43 +00:00
parent b1f0cf9278
commit 8bef20c24d
12 changed files with 243 additions and 231 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/ir_opt/constant_propagation_pass.cpp
View file

@ -16,9 +16,9 @@ namespace Optimization {
void ConstantPropagation(IR::Block& block, const UserCallbacks::Memory& memory_callbacks) {
for (auto& inst : block) {
switch (inst.GetOpcode()) {
case IR::Opcode::SetCFlag: {
case IR::Opcode::A32SetCFlag: {
IR::Value arg = inst.GetArg(0);
if (!arg.IsImmediate() && arg.GetInst()->GetOpcode() == IR::Opcode::GetCFlag) {
if (!arg.IsImmediate() && arg.GetInst()->GetOpcode() == IR::Opcode::A32GetCFlag) {
inst.Invalidate();
}
break;
@ -41,7 +41,7 @@ void ConstantPropagation(IR::Block& block, const UserCallbacks::Memory& memory_c
}
break;
}
case IR::Opcode::ReadMemory8: {
case IR::Opcode::A32ReadMemory8: {
if (!inst.AreAllArgsImmediates())
break;
@ -52,7 +52,7 @@ void ConstantPropagation(IR::Block& block, const UserCallbacks::Memory& memory_c
}
break;
}
case IR::Opcode::ReadMemory16: {
case IR::Opcode::A32ReadMemory16: {
if (!inst.AreAllArgsImmediates())
break;
@ -63,7 +63,7 @@ void ConstantPropagation(IR::Block& block, const UserCallbacks::Memory& memory_c
}
break;
}
case IR::Opcode::ReadMemory32: {
case IR::Opcode::A32ReadMemory32: {
if (!inst.AreAllArgsImmediates())
break;
@ -74,7 +74,7 @@ void ConstantPropagation(IR::Block& block, const UserCallbacks::Memory& memory_c
}
break;
}
case IR::Opcode::ReadMemory64: {
case IR::Opcode::A32ReadMemory64: {
if (!inst.AreAllArgsImmediates())
break;

32
src/ir_opt/get_set_elimination_pass.cpp
View file

@ -54,7 +54,7 @@ void GetSetElimination(IR::Block& block) {
for (auto inst = block.begin(); inst != block.end(); ++inst) {
switch (inst->GetOpcode()) {
case IR::Opcode::SetRegister: {
case IR::Opcode::A32SetRegister: {
A32::Reg reg = inst->GetArg(0).GetA32RegRef();
if (reg == A32::Reg::PC)
break;
@ -62,14 +62,14 @@ void GetSetElimination(IR::Block& block) {
do_set(reg_info[reg_index], inst->GetArg(1), inst);
break;
}
case IR::Opcode::GetRegister: {
case IR::Opcode::A32GetRegister: {
A32::Reg reg = inst->GetArg(0).GetA32RegRef();
ASSERT(reg != A32::Reg::PC);
size_t reg_index = static_cast<size_t>(reg);
do_get(reg_info[reg_index], inst);
break;
}
case IR::Opcode::SetExtendedRegister32: {
case IR::Opcode::A32SetExtendedRegister32: {
A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
size_t reg_index = A32::RegNumber(reg);
do_set(ext_reg_singles_info[reg_index], inst->GetArg(1), inst);
@ -80,7 +80,7 @@ void GetSetElimination(IR::Block& block) {
}
break;
}
case IR::Opcode::GetExtendedRegister32: {
case IR::Opcode::A32GetExtendedRegister32: {
A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
size_t reg_index = A32::RegNumber(reg);
do_get(ext_reg_singles_info[reg_index], inst);
@ -91,7 +91,7 @@ void GetSetElimination(IR::Block& block) {
}
break;
}
case IR::Opcode::SetExtendedRegister64: {
case IR::Opcode::A32SetExtendedRegister64: {
A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
size_t reg_index = A32::RegNumber(reg);
do_set(ext_reg_doubles_info[reg_index], inst->GetArg(1), inst);
@ -103,7 +103,7 @@ void GetSetElimination(IR::Block& block) {
}
break;
}
case IR::Opcode::GetExtendedRegister64: {
case IR::Opcode::A32GetExtendedRegister64: {
A32::ExtReg reg = inst->GetArg(0).GetA32ExtRegRef();
size_t reg_index = A32::RegNumber(reg);
do_get(ext_reg_doubles_info[reg_index], inst);
@ -115,43 +115,43 @@ void GetSetElimination(IR::Block& block) {
}
break;
}
case IR::Opcode::SetNFlag: {
case IR::Opcode::A32SetNFlag: {
do_set(cpsr_info.n, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetNFlag: {
case IR::Opcode::A32GetNFlag: {
do_get(cpsr_info.n, inst);
break;
}
case IR::Opcode::SetZFlag: {
case IR::Opcode::A32SetZFlag: {
do_set(cpsr_info.z, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetZFlag: {
case IR::Opcode::A32GetZFlag: {
do_get(cpsr_info.z, inst);
break;
}
case IR::Opcode::SetCFlag: {
case IR::Opcode::A32SetCFlag: {
do_set(cpsr_info.c, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetCFlag: {
case IR::Opcode::A32GetCFlag: {
do_get(cpsr_info.c, inst);
break;
}
case IR::Opcode::SetVFlag: {
case IR::Opcode::A32SetVFlag: {
do_set(cpsr_info.v, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetVFlag: {
case IR::Opcode::A32GetVFlag: {
do_get(cpsr_info.v, inst);
break;
}
case IR::Opcode::SetGEFlags: {
case IR::Opcode::A32SetGEFlags: {
do_set(cpsr_info.ge, inst->GetArg(0), inst);
break;
}
case IR::Opcode::GetGEFlags: {
case IR::Opcode::A32GetGEFlags: {
do_get(cpsr_info.ge, inst);
break;
}