TranslateArm: Implement UQSUB8.

src/backend_x64/emit_x64.cpp

@@ -1055,6 +1055,24 @@ void EmitX64::EmitByteReverseDual(IR::Block&, IR::Inst* inst) {
     code->BSWAP(64, result);
 }
 
+void EmitX64::EmitPackedSaturatedSubU8(IR::Block& block, IR::Inst* inst) {
+    IR::Value a = inst->GetArg(0);
+    IR::Value b = inst->GetArg(1);
+
+    X64Reg result = reg_alloc.UseDefRegister(a, inst, any_gpr);
+    OpArg op_arg = reg_alloc.UseOpArg(b, any_gpr);
+
+    X64Reg xmm_scratch_a = reg_alloc.ScratchRegister(any_xmm);
+    X64Reg xmm_scratch_b = reg_alloc.ScratchRegister(any_xmm);
+
+    code->MOVD_xmm(xmm_scratch_a, R(result));
+    code->MOVD_xmm(xmm_scratch_b, op_arg);
+
+    code->PSUBUSB(xmm_scratch_a, R(xmm_scratch_b));
+
+    code->MOVD_xmm(R(result), xmm_scratch_a);
+}
+
 static void DenormalsAreZero32(BlockOfCode* code, X64Reg xmm_value, X64Reg gpr_scratch) {
     // We need to report back whether we've found a denormal on input.
     // SSE doesn't do this for us when SSE's DAZ is enabled.

src/frontend/disassembler/disassembler_arm.cpp

@@ -673,7 +673,9 @@ public:
     std::string arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
     std::string arm_UQASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
     std::string arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
-    std::string arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
+    std::string arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
+        return Common::StringFromFormat("uqsub8%s %s, %s, %s", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
+    }
     std::string arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
 
     // Parallel Add/Subtract (Halving) instructions

src/frontend/ir/ir_emitter.cpp

@@ -282,6 +282,10 @@ IR::Value IREmitter::ByteReverseDual(const IR::Value& a) {
     return Inst(IR::Opcode::ByteReverseDual, {a});
 }
 
+IR::Value IREmitter::PackedSaturatedSubU8(const IR::Value& a, const IR::Value& b) {
+    return Inst(IR::Opcode::PackedSaturatedSubU8, {a, b});
+}
+
 IR::Value IREmitter::TransferToFP32(const IR::Value& a) {
     return Inst(IR::Opcode::TransferToFP32, {a});
 }

src/frontend/ir/ir_emitter.h

@@ -98,6 +98,7 @@ public:
     IR::Value ByteReverseWord(const IR::Value& a);
     IR::Value ByteReverseHalf(const IR::Value& a);
     IR::Value ByteReverseDual(const IR::Value& a);
+    IR::Value PackedSaturatedSubU8(const IR::Value& a, const IR::Value& b);
 
     IR::Value TransferToFP32(const IR::Value& a);
     IR::Value TransferToFP64(const IR::Value& a);

src/frontend/ir/opcodes.inc

@@ -60,6 +60,7 @@ OPCODE(ZeroExtendByteToWord,    T::U32,         T::U8
 OPCODE(ByteReverseWord,         T::U32,         T::U32                                          )
 OPCODE(ByteReverseHalf,         T::U16,         T::U16                                          )
 OPCODE(ByteReverseDual,         T::U64,         T::U64                                          )
+OPCODE(PackedSaturatedSubU8,    T::U32,         T::U32,         T::U32                          )
 
 // Floating-point
 OPCODE(TransferToFP32,          T::F32,         T::U32                                          )

src/frontend/translate/translate_arm/parallel.cpp

@@ -101,7 +101,11 @@ bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
-    return InterpretThisInstruction();
+    if (ConditionPassed(cond)) {
+        auto result = ir.PackedSaturatedSubU8(ir.GetRegister(n), ir.GetRegister(m));
+        ir.SetRegister(d, result);
+    }
+    return true;
 }
 
 bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {