Suyu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-01-08 15:38:19 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

A64: Implement PMULL{2}

Browse source
This commit is contained in:
Lioncash 2018-07-26 12:24:47 -04:00 • committed by MerryMage
parent 5ebf496d4e
commit 7fdd8b0197
6 changed files with 64 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -687,7 +687,7 @@ INST(SABDL, "SABDL, SABDL2", "0Q001
INST(SMLAL_vec, "SMLAL, SMLAL2 (vector)", "0Q001110zz1mmmmm100000nnnnnddddd")
INST(SMLSL_vec, "SMLSL, SMLSL2 (vector)", "0Q001110zz1mmmmm101000nnnnnddddd")
INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd")
//INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd")
INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_different.cpp
View file

@ -161,6 +161,22 @@ bool WideOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Ve
}
} // Anonymous namespace
bool TranslatorVisitor::PMULL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b01 || size == 0b10) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = 64;
const IR::U128 operand1 = Vpart(datasize, Vn, Q);
const IR::U128 operand2 = Vpart(datasize, Vm, Q);
const IR::U128 result = ir.VectorPolynomialMultiplyLong(esize, operand1, operand2);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::SABAL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return AbsoluteDifferenceLong(*this, Q, size, Vm, Vn, Vd, AbsoluteDifferenceBehavior::Accumulate, Signedness::Signed);
}

12
src/frontend/ir/ir_emitter.cpp
View file

@ -1198,6 +1198,18 @@ U128 IREmitter::VectorPolynomialMultiply(const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorPolynomialMultiply8, a, b);
}
U128 IREmitter::VectorPolynomialMultiplyLong(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorPolynomialMultiplyLong8, a, b);
case 64:
return Inst<U128>(Opcode::VectorPolynomialMultiplyLong64, a, b);
default:
UNREACHABLE();
return {};
}
}
U128 IREmitter::VectorPopulationCount(const U128& a) {
return Inst<U128>(Opcode::VectorPopulationCount, a);
}

1
src/frontend/ir/ir_emitter.h
View file

@ -239,6 +239,7 @@ public:
U128 VectorPairedAddSignedWiden(size_t original_esize, const U128& a);
U128 VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a);
U128 VectorPolynomialMultiply(const U128& a, const U128& b);
U128 VectorPolynomialMultiplyLong(size_t esize, const U128& a, const U128& b);
U128 VectorPopulationCount(const U128& a);
U128 VectorReverseBits(const U128& a);
U128 VectorRotateLeft(size_t esize, const U128& a, u8 amount);

2
src/frontend/ir/opcodes.inc
View file

@ -331,6 +331,8 @@ OPCODE(VectorPairedAdd16, T::U128, T::U128,
OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorPolynomialMultiply8, T::U128, T::U128, T::U128 )
OPCODE(VectorPolynomialMultiplyLong8, T::U128, T::U128, T::U128 )
OPCODE(VectorPolynomialMultiplyLong64, T::U128, T::U128, T::U128 )
OPCODE(VectorPopulationCount, T::U128, T::U128 )
OPCODE(VectorReverseBits, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddS8, T::U128, T::U128, T::U128 )