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A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated

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MerryMage 2018-04-04 10:28:52 +01:00
parent 5c95e28ed0
commit 7969871aa3
4 changed files with 39 additions and 3 deletions
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3
src/frontend/A64/translate/impl/impl.h
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@ -865,7 +865,8 @@ struct TranslatorVisitor final {
// Data Processing - FP and SIMD - SIMD modified immediate
bool MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<4> cmode, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
bool FMOV_2(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
bool FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
bool FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd);
// Data Processing - FP and SIMD - SIMD Shift by immediate
bool SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd);

34
src/frontend/A64/translate/impl/simd_modified_immediate.cpp
View file

@ -76,4 +76,36 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<
return true;
}
} // namespace Dynarmic::A64
bool TranslatorVisitor::FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
if (op && !Q) {
return UnallocatedEncoding();
}
const u64 imm64 = AdvSIMDExpandImm(op, Imm<4>{0b1111}, concatenate(a, b, c, d, e, f, g, h));
const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64));
V(128, Vd, imm);
return true;
}
bool TranslatorVisitor::FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const Imm<8> imm8 = concatenate(a, b, c, d, e, f, g, h);
const u16 imm16 = [&imm8]{
u16 imm16 = 0;
imm16 |= imm8.Bit<7>() ? 0x8000 : 0;
imm16 |= imm8.Bit<6>() ? 0x3000 : 0x4000;
imm16 |= imm8.Bits<0, 5, u16>() << 6;
return imm16;
}();
const u64 imm64 = Common::Replicate<u64>(imm16, 16);
const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64));
V(128, Vd, imm);
return true;
}
} // namespace Dynarmic::A6