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A32: Implement ASIMD VRSHL

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Lioncash 2020-06-19 13:46:19 -04:00 • committed by merry
parent 682621ef1a
commit 794440cf8d
3 changed files with 21 additions and 1 deletions
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19
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@ -268,6 +268,25 @@ bool ArmTranslatorVisitor::asimd_VQSHL_reg(bool U, bool D, size_t sz, size_t Vn,
return true;
}
bool ArmTranslatorVisitor::asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto n = ToVector(Q, Vn, N);
const auto reg_m = ir.GetVector(m);
const auto reg_n = ir.GetVector(n);
const auto result = U ? ir.VectorRoundingShiftLeftUnsigned(esize, reg_m, reg_n)
: ir.VectorRoundingShiftLeftSigned(esize, reg_m, reg_n);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();