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implemented other ic instructions

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This commit is contained in:
rufi 2020-11-09 09:01:20 +00:00 • committed by MerryMage
parent 8728444af8
commit 77621a8448
4 changed files with 24 additions and 38 deletions
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14
src/frontend/A64/translate/impl/sys_ic.cpp
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@ -7,21 +7,19 @@
namespace Dynarmic::A64 {
static bool InstructionCacheInstruction(TranslatorVisitor& v, InstructionCacheOperation op, const Reg Rt) {
v.ir.InstructionCacheOperationRaised(op, v.X(64, Rt));
bool TranslatorVisitor::IC_IALLU() {
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoU, ir.Imm64(0));
return true;
}
bool TranslatorVisitor::IC_IALLU() {
return false;
}
bool TranslatorVisitor::IC_IALLUIS() {
return false;
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoUInnerSharable, ir.Imm64(0));
return true;
}
bool TranslatorVisitor::IC_IVAU(Reg Rt) {
return InstructionCacheInstruction(*this, InstructionCacheOperation::InvalidateByVAToPoU, Rt);
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateByVAToPoU, X(64, Rt));
return true;
}
} // namespace Dynarmic::A64

25
src/frontend/ir/microinstruction.cpp
View file

@ -520,18 +520,19 @@ bool Inst::IsSetCheckBitOperation() const {
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64DataCacheOperationRaised ||
IsSetCheckBitOperation() ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
return op == Opcode::PushRSB ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64InstructionCacheOperationRaised ||
IsSetCheckBitOperation() ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction();
}